svn commit: r252032 - head/sys/amd64/include

[Konstantin Belousov]

On Sat, Jun 22, 2013 at 06:58:15PM +1000, Bruce Evans wrote:
> So the i386 version be simply "addl; adcl" to memory.  Each store in
> this is atomic at the per-CPU level.  If there is no carry, then the
> separate stores are equivalent to adding separate nonnegative values and
> the counter value is valid at all times.  If there is carry, then the
> separate stores are equivalent to adding a negative value followed by
> a larger positive value.  The counter transiently goes backwards, but
> no information is lost and the counter is eventually set to the correct
> forward-going value.

This is quite interesting idea, but I still did not decided if it
acceptable.  The issue is that we could add the carry to the other
processor counter, if the preemption kicks in at right time between
two instructions.  I did not found any argument why would it be
wrong, the races for fetch operation seems to be the same with either
local update method.

On the other hand, for debugging it would be quite confusing state of
the counters array to observe.
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