svn commit: r253161 - head/sys/dev/uart

John Baldwin jhb at
Wed Jul 10 18:05:48 UTC 2013

On Wednesday, July 10, 2013 1:42:20 pm Marcel Moolenaar wrote:
> Author: marcel
> Date: Wed Jul 10 17:42:20 2013
> New Revision: 253161
> URL:
> Log:
>   Protect against broken hardware. In this particular case, protect against
>   H/W not de-asserting the interrupt at all. On x86, and because of the
>   following conditions, this results in a hard hang with interrupts disabled:
>   1.  The uart(4) driver uses a spin lock to protect against concurrent
>       access to the H/W. Spin locks disable and restore interrupts.
>   2.  Restoring the interrupt on x86 always writes the flags register. Even
>       if we're restoring the interrupt from disabled to disabled.
>   3.  The x86 CPU has a short window in which interrupts are enabled when the
>       flags register is written.

Do you have proof of this?  I have never seen anything like this documented.
It would be fundamentally broken if true.  In fact, if anything the evidence
I have seen is the exact opposite: that Intel is very careful to prevent races
of this sort.  Specifically, Intel CPUs have long had a feature of disabling
interrupts for the instruction following POP SS to permit atomic loads of
SS:ESP (for code that doesn't use LSS).  I highly doubt your claim is true.

In fact, I think you might be confused by the VME bits (VIP and VIF). The
POPF instruction is documented to clear VIP and VIF, but those flags only
matter when operating in virtual 86 mode.  They are not relevant to our
kernel.  I think you need to find a real explanation for the hang you are

John Baldwin

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