svn commit: r244899 - head/sys/mips/beri

[Robert N. M. Watson]

On 1 Jan 2013, at 22:08, Andrew Turner wrote:

>> On a semi-related note: the current obstacle to moving more devices
>> over to using FDT on BERI is that our FDT implementation appears to
>> require a PIC to be configured. We're not actually using a PIC on
>> BERI currently. It works fine attached to nexus, as the implied
>> fallback for not having a PIC is to simply use the suitably numbered
>> interrupt wires direct into the MIPS. However, trying the same setup
>> described using FDT leads to an interrupt-related warning at boot,
>> and no interrupt being provided to the driver. I suspect I need to
>> provide a PIC-alike software component as a fall-back for the non-PIC
>> case. From a brief e-mail exchange with JC, it sounds like the XLP
>> FDT setup is actually not using interrupts either, currently.
> 
> I'm not sure if a PIC is required. From my reading of the code it
> appears not. By the look of it if you are using the nexus to
> handle interrupts you need to put an interrupts property in the device
> and "#interrupt-cells = <1>;" in the soc node.
> 
> You will also need to implement an interrupt decode function and add it
> to the fdt_pic_table array. ARM has a number of almost identical copies
> of this function you can use for inspration.


This seemed to do the trick; what do you think of the attached? This isn't a board-specific change, so I dropped it into the common fdt_mips.c code. On the other hand, this left it a bit open as to what the right compatible= line to use was, so feedback there most welcome.

Robert

Change 219933 by rwatson at rwatson_zenith_cl_cam_ac_uk on 2013/01/02 09:32:16

	Implement an FDT PIC decode routine to use when no PIC has been
	configured, which assumes a cascade back to the nexus bus (e.g.,
	the on-board CP0 interrupt management parts on the MIPS).  If the
	soc bus in a MIPS DTS file is declared as "mips4k,cp0"-compatible,
	then this will be enabled.  This is sufficient to allow IRQs to be
	configured on BERI.

Affected files ...

.. //depot/projects/ctsrd/beribsd/src/sys/dev/fdt/fdt_mips.c#2 edit

Differences ...

==== //depot/projects/ctsrd/beribsd/src/sys/dev/fdt/fdt_mips.c#2 (text+ko) ====

@@ -49,8 +49,26 @@
	{ NULL, NULL }
};

+/*
+ * For PIC-free boards, provide a PIC decoder to be used with mips4k CP0
+ * interrupt control directly.
+ */
+static int
+fdt_pic_decode_mips4k_cp0(phandle_t node, pcell_t *intr, int *interrupt,
+    int *trig, int *pol)
+{
+
+	if (!fdt_is_compatible(node, "mips4k,cp0"))
+		return (ENXIO);
+
+	*interrupt = fdt32_to_cpu(intr[0]);
+	*trig = INTR_TRIGGER_CONFORM;
+	*pol = INTR_POLARITY_CONFORM;
+
+	return (0);
+}
+
fdt_pic_decode_t fdt_pic_table[] = {
-	NULL,
-	NULL,
+	&fdt_pic_decode_mips4k_cp0,
	NULL
};