svn commit: r240471 - in head/sys/dev/ath/ath_hal: ar5416 ar9002

[Adrian Chadd]

Author: adrian
Date: Thu Sep 13 18:24:13 2012
New Revision: 240471
URL: http://svn.freebsd.org/changeset/base/240471

Log:
  Don't use AR_PHY_MODE to setup half/quarter rate.
  
  I'm not sure where in the deep, distant past I found the AR_PHY_MODE
  registers for half/quarter rate mode, but unfortunately that doesn't
  seem to work "right" for non-AR9280 chips.
  
  Specifically:
  
  * don't touch AR_PHY_MODE
  * set the PLL bits when configuring half/quarter rate
  
  I've verified this on the AR9280 (5ghz fast clock) and the AR5416.
  
  The AR9280 works in both half/quarter rate; the AR5416 unfortunately
  only currently works at half rate.  It fails to calibrate on quarter rate.

Modified:
  head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
  head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c	Thu Sep 13 17:49:11 2012	(r240470)
+++ head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c	Thu Sep 13 18:24:13 2012	(r240471)
@@ -746,19 +746,6 @@ ar5416SetRfMode(struct ath_hal *ah, cons
 			AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
 	}
 
-	/*
-	 * Set half/quarter mode flags if required.
-	 *
-	 * This doesn't change the IFS timings at all; that needs to
-	 * be done as part of the MAC setup.  Similarly, the PLL
-	 * configuration also needs some changes for the half/quarter
-	 * rate clock.
-	 */
-	if (IEEE80211_IS_CHAN_HALF(chan))
-		rfMode |= AR_PHY_MODE_HALF;
-	else if (IEEE80211_IS_CHAN_QUARTER(chan))
-		rfMode |= AR_PHY_MODE_QUARTER;
-
 	OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
 }
 

Modified: head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c	Thu Sep 13 17:49:11 2012	(r240470)
+++ head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c	Thu Sep 13 18:24:13 2012	(r240471)
@@ -114,6 +114,10 @@ ar9280InitPLL(struct ath_hal *ah, const 
 		 * Else, set PLL to 0x2850 to prevent reset-to-reset variation 
 		 */
 		pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850;
+		if (IEEE80211_IS_CHAN_HALF(chan))
+			pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
+		else if (IEEE80211_IS_CHAN_QUARTER(chan))
+			pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
 	} else if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
 		pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
 		if (chan != AH_NULL) {