svn commit: r237434 - in head/lib/libc: amd64/sys gen i386/sys include sys

[David Chisnall]

On 22 Jun 2012, at 08:34, Marius Strobl wrote:

> I don't know much about x86 CPUs but is my understanding correct
> that TSCs are not synchronized in any way across CPUs, i.e.
> reading it on different CPUs may result in time going backwards
> etc., which is okay for this application though?

As long as the initial value is set on every context switch, it only matters that the TSC is monotonic and increments at an approximately constant rate.  It is also possible to set the TSC value, but that's less useful in this context.

The one thing to be careful about is the fact that certain power saving states will affect the speed at which the TSC increments, and so it is important to update the ticks-per-second value whenever a core goes into a low power state.

This is more or less the same approach used by Xen, so most of the issues have been ironed out: Oracle complained to CPU vendors about a few corner cases and, because Oracle customers tend to buy a lot of expensive Xeon and Opteron chips, they were fixed quite promptly.  

David