svn commit: r236989 - head/sys/arm/at91

Warner Losh imp at FreeBSD.org
Wed Jun 13 04:52:20 UTC 2012


Author: imp
Date: Wed Jun 13 04:52:19 2012
New Revision: 236989
URL: http://svn.freebsd.org/changeset/base/236989

Log:
  Strip trailing whitespace before other changes.

Modified:
  head/sys/arm/at91/at91.c
  head/sys/arm/at91/at91_mci.c
  head/sys/arm/at91/at91_pio_rm9200.h
  head/sys/arm/at91/at91_pitreg.h
  head/sys/arm/at91/at91_pmcvar.h
  head/sys/arm/at91/at91_reset.S
  head/sys/arm/at91/at91_ssc.c
  head/sys/arm/at91/at91_wdtreg.h
  head/sys/arm/at91/at91rm9200.c
  head/sys/arm/at91/at91rm92reg.h
  head/sys/arm/at91/at91sam9260reg.h
  head/sys/arm/at91/at91sam9g20.c
  head/sys/arm/at91/at91sam9g20reg.h
  head/sys/arm/at91/board_qila9g20.c
  head/sys/arm/at91/board_sam9g20ek.c
  head/sys/arm/at91/if_macb.c
  head/sys/arm/at91/uart_cpu_at91rm9200usart.c

Modified: head/sys/arm/at91/at91.c
==============================================================================
--- head/sys/arm/at91/at91.c	Wed Jun 13 04:40:29 2012	(r236988)
+++ head/sys/arm/at91/at91.c	Wed Jun 13 04:52:19 2012	(r236989)
@@ -72,7 +72,7 @@ at91_bs_map(void *t, bus_addr_t bpa, bus
 	endpa = round_page(bpa + size);
 
 	*bshp = (vm_offset_t)pmap_mapdev(pa, endpa - pa);
-		       
+
 	return (0);
 }
 
@@ -98,7 +98,7 @@ at91_bs_subregion(void *t, bus_space_han
 }
 
 static void
-at91_barrier(void *t, bus_space_handle_t bsh, bus_size_t size, bus_size_t b, 
+at91_barrier(void *t, bus_space_handle_t bsh, bus_size_t size, bus_size_t b,
     int a)
 {
 }
@@ -272,7 +272,7 @@ at91_attach(device_t dev)
 
 	/* Our device list will be added automatically by the cpu device
 	 * e.g. at91rm9200.c when it is identified. To ensure that the
-	 * CPU and PMC are attached first any other "identified" devices 
+	 * CPU and PMC are attached first any other "identified" devices
 	 * call BUS_ADD_CHILD(9) with an "order" of at least 2. */
 
 	bus_generic_probe(dev);
@@ -357,8 +357,8 @@ at91_release_resource(device_t dev, devi
 
 static int
 at91_setup_intr(device_t dev, device_t child,
-    struct resource *ires, int flags, driver_filter_t *filt, 
-    driver_intr_t *intr, void *arg, void **cookiep)    
+    struct resource *ires, int flags, driver_filter_t *filt,
+    driver_intr_t *intr, void *arg, void **cookiep)
 {
 	struct at91_softc *sc = device_get_softc(dev);
 	int error;
@@ -381,7 +381,7 @@ at91_teardown_intr(device_t dev, device_
 {
 	struct at91_softc *sc = device_get_softc(dev);
 
-	bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 
+	bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR,
 	    1 << rman_get_start(res));
 	return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
 }
@@ -397,7 +397,7 @@ at91_activate_resource(device_t bus, dev
 	if (type == SYS_RES_MEMORY) {
 		error = bus_space_map(rman_get_bustag(r),
 		    rman_get_bushandle(r), rman_get_size(r), 0, &p);
-		if (error) 
+		if (error)
 			return (error);
 		rman_set_bushandle(r, p);
 	}
@@ -432,7 +432,7 @@ void
 arm_mask_irq(uintptr_t nb)
 {
 	
-	bus_space_write_4(at91_softc->sc_st, 
+	bus_space_write_4(at91_softc->sc_st,
 	    at91_softc->sc_aic_sh, IC_IDCR, 1 << nb);
 }
 
@@ -458,7 +458,7 @@ void
 arm_unmask_irq(uintptr_t nb)
 {
 	
-	bus_space_write_4(at91_softc->sc_st, 
+	bus_space_write_4(at91_softc->sc_st,
 	at91_softc->sc_aic_sh, IC_IECR, 1 << nb);
 	bus_space_write_4(at91_softc->sc_st, at91_softc->sc_aic_sh,
 	    IC_EOICR, 0);

Modified: head/sys/arm/at91/at91_mci.c
==============================================================================
--- head/sys/arm/at91/at91_mci.c	Wed Jun 13 04:40:29 2012	(r236988)
+++ head/sys/arm/at91/at91_mci.c	Wed Jun 13 04:52:19 2012	(r236989)
@@ -155,8 +155,8 @@ at91_mci_init(device_t dev)
 #ifndef  AT91_MCI_SLOT_B
 	WR4(sc, MCI_SDCR, 0);			/* SLOT A, 1 bit bus */
 #else
-	/* XXX Really should add second "unit" but nobody using using 
-	 * a two slot card that we know of. XXX */
+	/* XXX Really should add second "unit" but nobody using using
+	 * a two slot card that we know of. -- except they are... XXX */
 	WR4(sc, MCI_SDCR, 1);			/* SLOT B, 1 bit bus */
 #endif
 }

Modified: head/sys/arm/at91/at91_pio_rm9200.h
==============================================================================
--- head/sys/arm/at91/at91_pio_rm9200.h	Wed Jun 13 04:40:29 2012	(r236988)
+++ head/sys/arm/at91/at91_pio_rm9200.h	Wed Jun 13 04:52:19 2012	(r236989)
@@ -161,13 +161,13 @@
 #define	AT91C_PD1_ETX1     (AT91C_PIO_PD1) //  Ethernet MAC Transmit Data 1
 #define	AT91C_PD10_PCK3     (AT91C_PIO_PD10) //  PMC Programmable Clock Output 3
 #define	AT91C_PD10_TPS1     (AT91C_PIO_PD10) //  ETM ARM9 pipeline status 1
-#define	AT91C_PD11_         (AT91C_PIO_PD11) //  
+#define	AT91C_PD11_         (AT91C_PIO_PD11) //
 #define	AT91C_PD11_TPS2     (AT91C_PIO_PD11) //  ETM ARM9 pipeline status 2
-#define	AT91C_PD12_         (AT91C_PIO_PD12) //  
+#define	AT91C_PD12_         (AT91C_PIO_PD12) //
 #define	AT91C_PD12_TPK0     (AT91C_PIO_PD12) //  ETM Trace Packet 0
-#define	AT91C_PD13_         (AT91C_PIO_PD13) //  
+#define	AT91C_PD13_         (AT91C_PIO_PD13) //
 #define	AT91C_PD13_TPK1     (AT91C_PIO_PD13) //  ETM Trace Packet 1
-#define	AT91C_PD14_         (AT91C_PIO_PD14) //  
+#define	AT91C_PD14_         (AT91C_PIO_PD14) //
 #define	AT91C_PD14_TPK2     (AT91C_PIO_PD14) //  ETM Trace Packet 2
 #define	AT91C_PD15_TD0      (AT91C_PIO_PD15) //  SSC Transmit data
 #define	AT91C_PD15_TPK3     (AT91C_PIO_PD15) //  ETM Trace Packet 3

Modified: head/sys/arm/at91/at91_pitreg.h
==============================================================================
--- head/sys/arm/at91/at91_pitreg.h	Wed Jun 13 04:40:29 2012	(r236988)
+++ head/sys/arm/at91/at91_pitreg.h	Wed Jun 13 04:52:19 2012	(r236989)
@@ -28,7 +28,7 @@
 #ifndef ARM_AT91_AT91PITREG_H
 #define ARM_AT91_AT91PITREG_H
 
-#define PIT_MR		0x0 
+#define PIT_MR		0x0
 #define PIT_SR		0x4
 #define PIT_PIVR	0x8
 #define PIT_PIIR	0xc

Modified: head/sys/arm/at91/at91_pmcvar.h
==============================================================================
--- head/sys/arm/at91/at91_pmcvar.h	Wed Jun 13 04:40:29 2012	(r236988)
+++ head/sys/arm/at91/at91_pmcvar.h	Wed Jun 13 04:52:19 2012	(r236989)
@@ -28,7 +28,7 @@
 #ifndef ARM_AT91_AT91_PMCVAR_H
 #define ARM_AT91_AT91_PMCVAR_H
 
-struct at91_pmc_clock 
+struct at91_pmc_clock
 {
 	char		*name;
 	uint32_t	hz;

Modified: head/sys/arm/at91/at91_reset.S
==============================================================================
--- head/sys/arm/at91/at91_reset.S	Wed Jun 13 04:40:29 2012	(r236988)
+++ head/sys/arm/at91/at91_reset.S	Wed Jun 13 04:52:19 2012	(r236989)
@@ -10,21 +10,21 @@ __FBSDID("$FreeBSD$");
 #define RSTC_RCR  (AT91SAM9G20_BASE + \
 	AT91SAM9G20_RSTC_BASE + RST_CR)
 
-/* 
+/*
  * From AT91SAM9G20 Datasheet errata 44:3.5:
  *
  * When User Reset occurs durring SDRAM read acces, eh SDRAM clock is turned
  * off while data are ready to be read on the data bus. The SDRAM maintains
- * the data until the clock restarts. 
- * 
+ * the data until the clock restarts.
+ *
  * If the User reset is programed to assert a general reset, the data
  * maintained by the SDRAM leads to a data bus conflict and adversly affects
  * the boot memories connected to the EBI:
  *  + NAND Flash boot functionality, if the system boots out of internal ROM.
- *  + NOR Flash boot, if the system boots on an external memory connected to 
+ *  + NOR Flash boot, if the system boots on an external memory connected to
  *    the EBI CS0.
  *
- * Assembly code is mandatory for the following sequnce as ARM 
+ * Assembly code is mandatory for the following sequnce as ARM
  * instructions need to be piplined.
  *
  */
@@ -38,12 +38,12 @@ ENTRY(cpu_reset_sam9g20)
 
 	/* Change Refresh to block all data access */
 	ldr	r0, =SDRAM_TR
-	ldr	r1, =1 
+	ldr	r1, =1
 	str	r1, [r0]
 
 	/* Prepare power down command */
 	ldr	r0, =SDRAM_LPR
-	ldr	r1, =2 
+	ldr	r1, =2
 
 	/* Prepare proc_reset and periph reset */
 	ldr	r2, =RSTC_RCR

Modified: head/sys/arm/at91/at91_ssc.c
==============================================================================
--- head/sys/arm/at91/at91_ssc.c	Wed Jun 13 04:40:29 2012	(r236988)
+++ head/sys/arm/at91/at91_ssc.c	Wed Jun 13 04:52:19 2012	(r236989)
@@ -214,7 +214,7 @@ at91_ssc_intr(void *xsc)
 	return;
 }
 
-static int 
+static int
 at91_ssc_open(struct cdev *dev, int oflags, int devtype, struct thread *td)
 {
 	struct at91_ssc_softc *sc;

Modified: head/sys/arm/at91/at91_wdtreg.h
==============================================================================
--- head/sys/arm/at91/at91_wdtreg.h	Wed Jun 13 04:40:29 2012	(r236988)
+++ head/sys/arm/at91/at91_wdtreg.h	Wed Jun 13 04:52:19 2012	(r236989)
@@ -23,7 +23,7 @@
  * SUCH DAMAGE.
  */
 
-/* 
+/*
  * $FreeBSD$
  */
 

Modified: head/sys/arm/at91/at91rm9200.c
==============================================================================
--- head/sys/arm/at91/at91rm9200.c	Wed Jun 13 04:40:29 2012	(r236988)
+++ head/sys/arm/at91/at91rm9200.c	Wed Jun 13 04:52:19 2012	(r236989)
@@ -164,7 +164,7 @@ at91_add_child(device_t dev, int prio, c
 		bus_set_resource(kid, SYS_RES_IRQ, 1, irq1, 1);
 	if (irq2 != 0)
 		bus_set_resource(kid, SYS_RES_IRQ, 2, irq2, 1);
-	if (addr != 0 && addr < AT91RM92_BASE) 
+	if (addr != 0 && addr < AT91RM92_BASE)
 		addr += AT91RM92_BASE;
 	if (addr != 0)
 		bus_set_resource(kid, SYS_RES_MEMORY, 0, addr, size);
@@ -189,7 +189,7 @@ at91_pll_outb(int freq)
 
 	if (freq > 155000000)
 		return (0x0000);
-	else 
+	else
 		return (0x8000);
 }
 
@@ -241,7 +241,7 @@ at91_attach(device_t dev)
 	at91sc->sc_irq_system = AT91RM92_IRQ_SYSTEM;
 
 	for (i = 0; i < 32; i++) {
-		bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SVR + 
+		bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SVR +
 		    i * 4, i);
 		/* Priority. */
 		bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SMR + i * 4,

Modified: head/sys/arm/at91/at91rm92reg.h
==============================================================================
--- head/sys/arm/at91/at91rm92reg.h	Wed Jun 13 04:40:29 2012	(r236988)
+++ head/sys/arm/at91/at91rm92reg.h	Wed Jun 13 04:52:19 2012	(r236989)
@@ -34,9 +34,9 @@
 #define RM9200_PLL_A_MIN_OUT_FREQ	 80000000 /*  80 MHz */
 #define RM9200_PLL_A_MAX_OUT_FREQ	180000000 /* 180 MHz */
 #define RM9200_PLL_A_MUL_SHIFT 16
-#define RM9200_PLL_A_MUL_MASK 0x7FF 
+#define RM9200_PLL_A_MUL_MASK 0x7FF
 #define RM9200_PLL_A_DIV_SHIFT 0
-#define RM9200_PLL_A_DIV_MASK 0xFF 
+#define RM9200_PLL_A_DIV_MASK 0xFF
 
 /*
  * PLL B input frequency spec sheet says it must be between 1MHz and 32MHz,
@@ -51,10 +51,11 @@
 #define RM9200_PLL_B_MIN_OUT_FREQ	 30000000 /*  30 MHz */
 #define RM9200_PLL_B_MAX_OUT_FREQ	240000000 /* 240 MHz */
 #define RM9200_PLL_B_MUL_SHIFT 16
-#define RM9200_PLL_B_MUL_MASK 0x7FF 
+#define RM9200_PLL_B_MUL_MASK 0x7FF
 #define RM9200_PLL_B_DIV_SHIFT 0
-#define RM9200_PLL_B_DIV_MASK 0xFF 
-/* 
+#define RM9200_PLL_B_DIV_MASK 0xFF
+
+/*
  * Memory map, from datasheet :
  * 0x00000000 - 0x0ffffffff : Internal Memories
  * 0x10000000 - 0x1ffffffff : Chip Select 0
@@ -112,7 +113,7 @@
 
 /* IRQs : */
 /*
- * 0: AIC 
+ * 0: AIC
  * 1: System peripheral (System timer, RTC, DBGU)
  * 2: PIO Controller A
  * 3: PIO Controller B

Modified: head/sys/arm/at91/at91sam9260reg.h
==============================================================================
--- head/sys/arm/at91/at91sam9260reg.h	Wed Jun 13 04:40:29 2012	(r236988)
+++ head/sys/arm/at91/at91sam9260reg.h	Wed Jun 13 04:52:19 2012	(r236989)
@@ -34,9 +34,9 @@
 #define SAM9260_PLL_A_MIN_OUT_FREQ	 80000000 /*  80 Mhz */
 #define SAM9260_PLL_A_MAX_OUT_FREQ	240000000 /* 240 Mhz */
 #define SAM9260_PLL_A_MUL_SHIFT 16
-#define SAM9260_PLL_A_MUL_MASK 0x3FF 
+#define SAM9260_PLL_A_MUL_MASK 0x3FF
 #define SAM9260_PLL_A_DIV_SHIFT 0
-#define SAM9260_PLL_A_DIV_MASK 0xFF 
+#define SAM9260_PLL_A_DIV_MASK 0xFF
 
 #define SAM9260_PLL_B_MIN_IN_FREQ	  1000000 /*   1 Mhz */
 #define SAM9260_PLL_B_MAX_IN_FREQ	  5000000 /*   5 Mhz */
@@ -45,9 +45,9 @@
 #define SAM9260_PLL_B_MUL_SHIFT 16
 #define SAM9260_PLL_B_MUL_MASK 0x3FF
 #define SAM9260_PLL_B_DIV_SHIFT 0
-#define SAM9260_PLL_B_DIV_MASK 0xFF 
+#define SAM9260_PLL_B_DIV_MASK 0xFF
 
-/* 
+/*
  * Memory map, from datasheet :
  * 0x00000000 - 0x0ffffffff : Internal Memories
  * 0x10000000 - 0x1ffffffff : Chip Select 0
@@ -73,7 +73,6 @@
 
 
 #define AT91SAM9260_BASE	0xd0000000
-                                 
 
 #define AT91SAM9260_EMAC_BASE 0xffc4000
 #define AT91SAM9260_EMAC_SIZE 0x4000
@@ -156,7 +155,7 @@
 #define AT91RM92_PMC_SIZE	0x100
 /* IRQs : */
 /*
- * 0: AIC 
+ * 0: AIC
  * 1: System peripheral (System timer, RTC, DBGU)
  * 2: PIO Controller A
  * 3: PIO Controller B

Modified: head/sys/arm/at91/at91sam9g20.c
==============================================================================
--- head/sys/arm/at91/at91sam9g20.c	Wed Jun 13 04:40:29 2012	(r236988)
+++ head/sys/arm/at91/at91sam9g20.c	Wed Jun 13 04:52:19 2012	(r236989)
@@ -157,7 +157,7 @@ at91_add_child(device_t dev, int prio, c
 		bus_set_resource(kid, SYS_RES_IRQ, 1, irq1, 1);
 	if (irq2 != 0)
 		bus_set_resource(kid, SYS_RES_IRQ, 2, irq2, 1);
-	if (addr != 0 && addr < AT91SAM9G20_BASE) 
+	if (addr != 0 && addr < AT91SAM9G20_BASE)
 		addr += AT91SAM9G20_BASE;
 	if (addr != 0)
 		bus_set_resource(kid, SYS_RES_MEMORY, 0, addr, size);
@@ -231,7 +231,7 @@ at91_attach(device_t dev)
 	sc->sc_sh = at91sc->sc_sh;
 	sc->dev = dev;
 
-	/* 
+	/*
 	 * XXX These values work for the RM9200, SAM926[01], and SAM9G20
 	 * will have to fix this when we want to support anything else. XXX
 	 */
@@ -252,7 +252,7 @@ at91_attach(device_t dev)
 	at91sc->sc_irq_system = AT91SAM9G20_IRQ_SYSTEM;
 
 	for (i = 0; i < 32; i++) {
-		bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SVR + 
+		bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SVR +
 		    i * 4, i);
 		/* Priority. */
 		bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SMR + i * 4,
@@ -281,7 +281,7 @@ at91_attach(device_t dev)
 	i = bus_space_read_4(sc->sc_st, sc->sc_matrix_sh,
 	    AT91SAM9G20_EBICSA);
 	bus_space_write_4(sc->sc_st, sc->sc_matrix_sh,
-	    AT91SAM9G20_EBICSA, 
+	    AT91SAM9G20_EBICSA,
 	    i | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
 
 

Modified: head/sys/arm/at91/at91sam9g20reg.h
==============================================================================
--- head/sys/arm/at91/at91sam9g20reg.h	Wed Jun 13 04:40:29 2012	(r236988)
+++ head/sys/arm/at91/at91sam9g20reg.h	Wed Jun 13 04:52:19 2012	(r236989)
@@ -35,20 +35,20 @@
 #define SAM9G20_PLL_A_MIN_OUT_FREQ	400000000 /* 400 Mhz */
 #define SAM9G20_PLL_A_MAX_OUT_FREQ	800000000 /* 800 Mhz */
 #define SAM9G20_PLL_A_MUL_SHIFT 16
-#define SAM9G20_PLL_A_MUL_MASK 0xFF 
+#define SAM9G20_PLL_A_MUL_MASK 0xFF
 #define SAM9G20_PLL_A_DIV_SHIFT 0
-#define SAM9G20_PLL_A_DIV_MASK 0xFF 
+#define SAM9G20_PLL_A_DIV_MASK 0xFF
 
 #define SAM9G20_PLL_B_MIN_IN_FREQ	  2000000 /*   2 Mhz */
 #define SAM9G20_PLL_B_MAX_IN_FREQ	 32000000 /*  32 Mhz */
 #define SAM9G20_PLL_B_MIN_OUT_FREQ	 30000000 /*  30 Mhz */
 #define SAM9G20_PLL_B_MAX_OUT_FREQ	100000000 /* 100 Mhz */
 #define SAM9G20_PLL_B_MUL_SHIFT 16
-#define SAM9G20_PLL_B_MUL_MASK 0x3F 
+#define SAM9G20_PLL_B_MUL_MASK 0x3F
 #define SAM9G20_PLL_B_DIV_SHIFT 0
-#define SAM9G20_PLL_B_DIV_MASK 0xFF 
+#define SAM9G20_PLL_B_DIV_MASK 0xFF
 
-/* 
+/*
  * Memory map, from datasheet :
  * 0x00000000 - 0x0ffffffff : Internal Memories
  * 0x10000000 - 0x1ffffffff : Chip Select 0
@@ -74,7 +74,6 @@
 
 
 #define AT91SAM9G20_BASE	0xd0000000
-                                 
 
 #define AT91SAM9G20_EMAC_BASE 0xffc4000
 #define AT91SAM9G20_EMAC_SIZE 0x4000
@@ -157,7 +156,7 @@
 #define AT91RM92_PMC_SIZE	0x100
 /* IRQs : */
 /*
- * 0: AIC 
+ * 0: AIC
  * 1: System peripheral (System timer, RTC, DBGU)
  * 2: PIO Controller A
  * 3: PIO Controller B

Modified: head/sys/arm/at91/board_qila9g20.c
==============================================================================
--- head/sys/arm/at91/board_qila9g20.c	Wed Jun 13 04:40:29 2012	(r236988)
+++ head/sys/arm/at91/board_qila9g20.c	Wed Jun 13 04:52:19 2012	(r236989)
@@ -24,7 +24,7 @@
  */
 
 /* Calao Systems QIL-9G20-Cxx
- * http://www.calao-systems.com 
+ * http://www.calao-systems.com
  */
 
 #include <sys/cdefs.h>

Modified: head/sys/arm/at91/board_sam9g20ek.c
==============================================================================
--- head/sys/arm/at91/board_sam9g20ek.c	Wed Jun 13 04:40:29 2012	(r236988)
+++ head/sys/arm/at91/board_sam9g20ek.c	Wed Jun 13 04:52:19 2012	(r236989)
@@ -23,9 +23,9 @@
  * SUCH DAMAGE.
  */
 
-/* 
+/*
  * This board file can be used for both:
- * Atmel SAM9G20-EK Development Card 
+ * Atmel SAM9G20-EK Development Card
  */
 
 #include <sys/cdefs.h>
@@ -69,7 +69,7 @@ board_init(void)
 	at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA24_TWCK, 1);
 
 #if 1
-	/* 
+	/*
 	 * Turn off Clock to DataFlash, conflicts with MCI clock.
 	 */
 	at91_pio_use_gpio(AT91SAM9G20_PIOA_BASE,AT91C_PIO_PA2);

Modified: head/sys/arm/at91/if_macb.c
==============================================================================
--- head/sys/arm/at91/if_macb.c	Wed Jun 13 04:40:29 2012	(r236988)
+++ head/sys/arm/at91/if_macb.c	Wed Jun 13 04:52:19 2012	(r236989)
@@ -730,7 +730,7 @@ macb_rx(struct macb_softc *sc)
 
 		m = sc->rx_desc[sc->rx_cons].buff;
 
-		bus_dmamap_sync(sc->dmatag_ring_rx, 
+		bus_dmamap_sync(sc->dmatag_ring_rx,
 		    sc->rx_desc[sc->rx_cons].dmamap, BUS_DMASYNC_POSTREAD);
 		if (macb_new_rxbuf(sc, sc->rx_cons) != 0) {
 			ifp->if_iqdrops++;
@@ -739,7 +739,7 @@ macb_rx(struct macb_softc *sc)
 			do  {
 				rxdesc->flags = DATA_SIZE;
 				MACB_DESC_INC(sc->rx_cons, MACB_MAX_RX_BUFFERS);
-				if ((rxdesc->flags & RD_EOF) != 0) 
+				if ((rxdesc->flags & RD_EOF) != 0)
 					break;
 				rxdesc = &(sc->desc_rx[sc->rx_cons]);
 			} while (sc->rx_cons != first);
@@ -776,7 +776,7 @@ macb_rx(struct macb_softc *sc)
 			if (nsegs > 1) {
 				sc->macb_cdata.rxtail->m_len = (rxbytes -
 				    ((nsegs - 1) * DATA_SIZE)) + 2;
-			} 
+			}
 
 			m = sc->macb_cdata.rxhead;
 			m->m_flags |= M_PKTHDR;
@@ -1102,7 +1102,7 @@ set_filter(struct macb_softc *sc)
 	int count;
 	uint32_t multicast_filter[2];
 
-	ifp = sc->ifp;       
+	ifp = sc->ifp;
 
 	config = read_4(sc, EMAC_NCFGR);
 	
@@ -1132,7 +1132,7 @@ set_filter(struct macb_softc *sc)
 		if (ifma->ifma_addr->sa_family != AF_LINK)
 			continue;
 		count++;
-		set_mac_filter(multicast_filter, 
+		set_mac_filter(multicast_filter,
 			   LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
 	}
 	if (count) {
@@ -1501,7 +1501,7 @@ macb_miibus_statchg(device_t dev)
 
 	mii = device_get_softc(sc->miibus);
 
-	sc->flags &= ~MACB_FLAG_LINK;       
+	sc->flags &= ~MACB_FLAG_LINK;
 
 	config = read_4(sc, EMAC_NCFGR);
 

Modified: head/sys/arm/at91/uart_cpu_at91rm9200usart.c
==============================================================================
--- head/sys/arm/at91/uart_cpu_at91rm9200usart.c	Wed Jun 13 04:40:29 2012	(r236988)
+++ head/sys/arm/at91/uart_cpu_at91rm9200usart.c	Wed Jun 13 04:52:19 2012	(r236989)
@@ -69,7 +69,7 @@ uart_cpu_getdev(int devtype, struct uart
 	di->ops = uart_getops(class);
 	di->bas.chan = 0;
 	di->bas.bst = &at91_bs_tag;
-	/* 
+	/*
 	 * XXX: Not pretty, but will work because we map the needed addresses
 	 * early.
 	 */


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