svn commit: r222392 - head/sys/powerpc/booke

[Marcel Moolenaar]

Author: marcel
Date: Fri May 27 23:18:41 2011
New Revision: 222392
URL: http://svn.freebsd.org/changeset/base/222392

Log:
  o   The P1020(E) & P2020(E) also have two cores. This conditional has
      a tendency to grow unwieldy so we may want to revisit this in due
      time.
  o   Simplify the CPU reset function by writing to the reset control
      register irrespective of whether the CPU has one and automatically
      falling back to the debug control register if we didn't reset the
      CPU. The side-effect is that we now properly reset future processors
      without first having to add the system version to the list.

Modified:
  head/sys/powerpc/booke/platform_bare.c

Modified: head/sys/powerpc/booke/platform_bare.c
==============================================================================
--- head/sys/powerpc/booke/platform_bare.c	Fri May 27 23:09:12 2011	(r222391)
+++ head/sys/powerpc/booke/platform_bare.c	Fri May 27 23:18:41 2011	(r222392)
@@ -104,7 +104,10 @@ bare_probe(platform_t plat)
 	int i, law_max, tgt;
 
 	ver = SVR_VER(mfspr(SPR_SVR));
-	if (ver == SVR_MPC8572E || ver == SVR_MPC8572)
+
+	if (ver == SVR_MPC8572E || ver == SVR_MPC8572 ||
+	    ver == SVR_P1020E || ver == SVR_P1020 ||
+	    ver == SVR_P2020E || ver == SVR_P2020)
 		maxcpu = 2;
 	else
 		maxcpu = 1;
@@ -280,24 +283,23 @@ bare_smp_start_cpu(platform_t plat, stru
 static void
 e500_reset(platform_t plat)
 {
-	uint32_t ver = SVR_VER(mfspr(SPR_SVR));
 
-	if (ver == SVR_MPC8572E || ver == SVR_MPC8572 ||
-	    ver == SVR_MPC8548E || ver == SVR_MPC8548)
-		/* Systems with dedicated reset register */
-		ccsr_write4(OCP85XX_RSTCR, 2);
-	else {
-		/* Clear DBCR0, disables debug interrupts and events. */
-		mtspr(SPR_DBCR0, 0);
-		__asm __volatile("isync");
-
-		/* Enable Debug Interrupts in MSR. */
-		mtmsr(mfmsr() | PSL_DE);
-
-		/* Enable debug interrupts and issue reset. */
-		mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM |
-		    DBCR0_RST_SYSTEM);
-	}
+	/*
+	 * Try the dedicated reset register first.
+	 * If the SoC doesn't have one, we'll fall
+	 * back to using the debug control register.
+	 */
+	ccsr_write4(OCP85XX_RSTCR, 2);
+
+	/* Clear DBCR0, disables debug interrupts and events. */
+	mtspr(SPR_DBCR0, 0);
+	__asm __volatile("isync");
+
+	/* Enable Debug Interrupts in MSR. */
+	mtmsr(mfmsr() | PSL_DE);
+
+	/* Enable debug interrupts and issue reset. */
+	mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM);
 
 	printf("Reset failed...\n");
 	while (1);