svn commit: r213498 - head/sys/arm/at91
Olivier Houchard
cognet at FreeBSD.org
Wed Oct 6 22:40:28 UTC 2010
Author: cognet
Date: Wed Oct 6 22:40:27 2010
New Revision: 213498
URL: http://svn.freebsd.org/changeset/base/213498
Log:
Add support for the AT91SAM9260
Submitted by: Greg Ansley
Added:
head/sys/arm/at91/at91sam9260.c (contents, props changed)
head/sys/arm/at91/at91sam9260reg.h (contents, props changed)
head/sys/arm/at91/board_qila9g20.c (contents, props changed)
head/sys/arm/at91/std.qila9g20 (contents, props changed)
Modified:
head/sys/arm/at91/at91_machdep.c
head/sys/arm/at91/at91_pio_sam9g20.h
head/sys/arm/at91/at91_pmc.c
head/sys/arm/at91/at91_pmcreg.h
head/sys/arm/at91/at91_rst.c
head/sys/arm/at91/at91sam9g20.c
head/sys/arm/at91/board_sam9g20ek.c
head/sys/arm/at91/files.at91sam9
head/sys/arm/at91/std.at91sam9
head/sys/arm/at91/std.sam9g20ek
Modified: head/sys/arm/at91/at91_machdep.c
==============================================================================
--- head/sys/arm/at91/at91_machdep.c Wed Oct 6 22:32:31 2010 (r213497)
+++ head/sys/arm/at91/at91_machdep.c Wed Oct 6 22:40:27 2010 (r213498)
@@ -368,8 +368,6 @@ initarm(void *arg, void *arg2)
(AT91_BASE + AT91_DBGU_BASE + DBGU_C1R);
memsize = board_init();
-
- printf("memsize = %d\n", memsize);
physmem = memsize / PAGE_SIZE;
/*
Modified: head/sys/arm/at91/at91_pio_sam9g20.h
==============================================================================
--- head/sys/arm/at91/at91_pio_sam9g20.h Wed Oct 6 22:32:31 2010 (r213497)
+++ head/sys/arm/at91/at91_pio_sam9g20.h Wed Oct 6 22:40:27 2010 (r213498)
@@ -1,6 +1,9 @@
/*
* Theses defines come from an atmel file that says specifically that it
* has no copyright.
+ *
+ * These defines are also usable for the AT91SAM9260 which has pin multiplexing
+ * that is identical to the AT91SAM9G20.
*/
/* $FreeBSD$ */
Modified: head/sys/arm/at91/at91_pmc.c
==============================================================================
--- head/sys/arm/at91/at91_pmc.c Wed Oct 6 22:32:31 2010 (r213497)
+++ head/sys/arm/at91/at91_pmc.c Wed Oct 6 22:40:27 2010 (r213498)
@@ -331,6 +331,9 @@ at91_pmc_pll_rate(struct at91_pmc_clock
div = (reg >> clk->pll_div_shift) & clk->pll_div_mask;
mul = (reg >> clk->pll_mul_shift) & clk->pll_mul_mask;
+// printf("pll = (%d / %d) * %d = %d\n",
+// freq, div ,mul + 1, (freq/div) * (mul+1));
+
if (div != 0 && mul != 0) {
freq /= div;
freq *= mul + 1;
@@ -338,6 +341,8 @@ at91_pmc_pll_rate(struct at91_pmc_clock
freq = 0;
}
clk->hz = freq;
+
+
return (freq);
}
@@ -444,7 +449,8 @@ at91_pmc_init_clock(struct at91_pmc_soft
mdiv = (mckr & PMC_MCKR_MDIV_MASK) >> 8;
if (at91_is_sam9()) {
- mck.hz /= (mdiv) ? (mdiv * 2) : 1;
+ if (mdiv > 0)
+ mck.hz /= mdiv * 2;
} else
mck.hz /= (1 + mdiv);
Modified: head/sys/arm/at91/at91_pmcreg.h
==============================================================================
--- head/sys/arm/at91/at91_pmcreg.h Wed Oct 6 22:32:31 2010 (r213497)
+++ head/sys/arm/at91/at91_pmcreg.h Wed Oct 6 22:40:27 2010 (r213498)
@@ -89,7 +89,7 @@
/* PMC Clock Generator Master Clock Register */
#define PMC_MCKR_PDIV (1 << 12) /* SAM9G20 Only */
#define PMC_MCKR_PLLADIV2 (1 << 12) /* SAM9G45 Only */
-#define PMC_MCKR_CSS_MASK (3 << 8)
+#define PMC_MCKR_CSS_MASK (3 << 0)
#define PMC_MCKR_MDIV_MASK (3 << 8)
#define PMC_MCKR_PRES_MASK (7 << 2)
Modified: head/sys/arm/at91/at91_rst.c
==============================================================================
--- head/sys/arm/at91/at91_rst.c Wed Oct 6 22:32:31 2010 (r213497)
+++ head/sys/arm/at91/at91_rst.c Wed Oct 6 22:40:27 2010 (r213498)
@@ -198,8 +198,8 @@ cpu_reset(void)
{
if (rst_sc) {
- if (at91_cpu_is(AT91_CPU_SAM9G20))
- cpu_reset_sam9g20();
+
+ cpu_reset_sam9g20(); /* May be null */
WR4(rst_sc, RST_MR,
RST_MR_ERSTL(0xd) | RST_MR_URSTEN | RST_MR_KEY);
Added: head/sys/arm/at91/at91sam9260.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/at91/at91sam9260.c Wed Oct 6 22:40:27 2010 (r213498)
@@ -0,0 +1,343 @@
+/*-
+ * Copyright (c) 2005 Olivier Houchard. All rights reserved.
+ * Copyright (c) 2010 Greg Ansley. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+
+#define _ARM32_BUS_DMA_PRIVATE
+#include <machine/bus.h>
+
+#include <arm/at91/at91var.h>
+#include <arm/at91/at91_aicreg.h>
+#include <arm/at91/at91sam9260reg.h>
+#include <arm/at91/at91_pmcreg.h>
+#include <arm/at91/at91_pmcvar.h>
+
+struct at91sam9_softc {
+ device_t dev;
+ bus_space_tag_t sc_st;
+ bus_space_handle_t sc_sh;
+ bus_space_handle_t sc_sys_sh;
+ bus_space_handle_t sc_aic_sh;
+ bus_space_handle_t sc_dbg_sh;
+ bus_space_handle_t sc_matrix_sh;
+};
+
+/*
+ * Standard priority levels for the system. 0 is lowest and 7 is highest.
+ * These values are the ones Atmel uses for its Linux port
+ */
+static const int at91_irq_prio[32] =
+{
+ 7, /* Advanced Interrupt Controller */
+ 7, /* System Peripherals */
+ 1, /* Parallel IO Controller A */
+ 1, /* Parallel IO Controller B */
+ 1, /* Parallel IO Controller C */
+ 0, /* Analog-to-Digital Converter */
+ 5, /* USART 0 */
+ 5, /* USART 1 */
+ 5, /* USART 2 */
+ 0, /* Multimedia Card Interface */
+ 2, /* USB Device Port */
+ 6, /* Two-Wire Interface */
+ 5, /* Serial Peripheral Interface 0 */
+ 5, /* Serial Peripheral Interface 1 */
+ 5, /* Serial Synchronous Controller */
+ 0, /* (reserved) */
+ 0, /* (reserved) */
+ 0, /* Timer Counter 0 */
+ 0, /* Timer Counter 1 */
+ 0, /* Timer Counter 2 */
+ 2, /* USB Host port */
+ 3, /* Ethernet */
+ 0, /* Image Sensor Interface */
+ 5, /* USART 3 */
+ 5, /* USART 4 */
+ 5, /* USART 5 */
+ 0, /* Timer Counter 3 */
+ 0, /* Timer Counter 4 */
+ 0, /* Timer Counter 5 */
+ 0, /* Advanced Interrupt Controller IRQ0 */
+ 0, /* Advanced Interrupt Controller IRQ1 */
+ 0, /* Advanced Interrupt Controller IRQ2 */
+};
+
+#define DEVICE(_name, _id, _unit) \
+ { \
+ _name, _unit, \
+ AT91SAM9260_ ## _id ##_BASE, \
+ AT91SAM9260_ ## _id ## _SIZE, \
+ AT91SAM9260_IRQ_ ## _id \
+ }
+
+static const struct cpu_devs at91_devs[] =
+{
+ DEVICE("at91_pmc", PMC, 0),
+ DEVICE("at91_wdt", WDT, 0),
+ DEVICE("at91_rst", RSTC, 0),
+ DEVICE("at91_pit", PIT, 0),
+ DEVICE("at91_pio", PIOA, 0),
+ DEVICE("at91_pio", PIOB, 1),
+ DEVICE("at91_pio", PIOC, 2),
+ DEVICE("at91_twi", TWI, 0),
+ DEVICE("at91_mci", MCI, 0),
+ DEVICE("uart", DBGU, 0),
+ DEVICE("uart", USART0, 1),
+ DEVICE("uart", USART1, 2),
+ DEVICE("uart", USART2, 3),
+ DEVICE("uart", USART3, 4),
+ DEVICE("uart", USART4, 5),
+ DEVICE("uart", USART5, 6),
+ DEVICE("spi", SPI0, 0),
+ DEVICE("spi", SPI1, 1),
+ DEVICE("ate", EMAC, 0),
+ DEVICE("macb", EMAC, 0),
+ DEVICE("nand", NAND, 0),
+ DEVICE("ohci", OHCI, 0),
+ { 0, 0, 0, 0, 0 }
+};
+
+static void
+at91_add_child(device_t dev, int prio, const char *name, int unit,
+ bus_addr_t addr, bus_size_t size, int irq0, int irq1, int irq2)
+{
+ device_t kid;
+ struct at91_ivar *ivar;
+
+ kid = device_add_child_ordered(dev, prio, name, unit);
+ if (kid == NULL) {
+ printf("Can't add child %s%d ordered\n", name, unit);
+ return;
+ }
+ ivar = malloc(sizeof(*ivar), M_DEVBUF, M_NOWAIT | M_ZERO);
+ if (ivar == NULL) {
+ device_delete_child(dev, kid);
+ printf("Can't add alloc ivar\n");
+ return;
+ }
+ device_set_ivars(kid, ivar);
+ resource_list_init(&ivar->resources);
+ if (irq0 != -1) {
+ bus_set_resource(kid, SYS_RES_IRQ, 0, irq0, 1);
+ if (irq0 != AT91SAM9260_IRQ_SYSTEM)
+ at91_pmc_clock_add(device_get_nameunit(kid), irq0, 0);
+ }
+ if (irq1 != 0)
+ bus_set_resource(kid, SYS_RES_IRQ, 1, irq1, 1);
+ if (irq2 != 0)
+ bus_set_resource(kid, SYS_RES_IRQ, 2, irq2, 1);
+ if (addr != 0 && addr < AT91SAM9260_BASE)
+ addr += AT91SAM9260_BASE;
+ if (addr != 0)
+ bus_set_resource(kid, SYS_RES_MEMORY, 0, addr, size);
+}
+
+static void
+at91_cpu_add_builtin_children(device_t dev)
+{
+ int i;
+ const struct cpu_devs *walker;
+
+ for (i = 1, walker = at91_devs; walker->name; i++, walker++) {
+ at91_add_child(dev, i, walker->name, walker->unit,
+ walker->mem_base, walker->mem_len, walker->irq0,
+ walker->irq1, walker->irq2);
+ }
+}
+
+static uint32_t
+at91_pll_outa(int freq)
+{
+
+ if (freq > 195000000)
+ return (0x20000000);
+ else
+ return (0x20008000);
+}
+
+static uint32_t
+at91_pll_outb(int freq)
+{
+ return (0x4000);
+}
+
+static void
+at91_identify(driver_t *drv, device_t parent)
+{
+
+ if (at91_cpu_is(AT91_CPU_SAM9260)) {
+ at91_add_child(parent, 0, "at91sam9260", 0, 0, 0, -1, 0, 0);
+ at91_cpu_add_builtin_children(parent);
+ }
+}
+
+static int
+at91_probe(device_t dev)
+{
+
+ if (at91_cpu_is(AT91_CPU_SAM9260)) {
+ device_set_desc(dev, "AT91SAM9260");
+ return (0);
+ }
+ return (ENXIO);
+}
+
+static int
+at91_attach(device_t dev)
+{
+ struct at91_pmc_clock *clk;
+ struct at91sam9_softc *sc = device_get_softc(dev);
+ int i;
+
+ struct at91_softc *at91sc = device_get_softc(device_get_parent(dev));
+
+ sc->sc_st = at91sc->sc_st;
+ sc->sc_sh = at91sc->sc_sh;
+ sc->dev = dev;
+
+ /*
+ * XXX These values work for the RM9200, SAM926[01], and SAM9260
+ * will have to fix this when we want to support anything else. XXX
+ */
+ if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9260_SYS_BASE,
+ AT91SAM9260_SYS_SIZE, &sc->sc_sys_sh) != 0)
+ panic("Enable to map system registers");
+
+ if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9260_DBGU_BASE,
+ AT91SAM9260_DBGU_SIZE, &sc->sc_dbg_sh) != 0)
+ panic("Enable to map DBGU registers");
+
+ if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9260_AIC_BASE,
+ AT91SAM9260_AIC_SIZE, &sc->sc_aic_sh) != 0)
+ panic("Enable to map system registers");
+
+ /* XXX Hack to tell atmelarm about the AIC */
+ at91sc->sc_aic_sh = sc->sc_aic_sh;
+ at91sc->sc_irq_system = AT91SAM9260_IRQ_SYSTEM;
+
+ for (i = 0; i < 32; i++) {
+ bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SVR +
+ i * 4, i);
+ /* Priority. */
+ bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SMR + i * 4,
+ at91_irq_prio[i]);
+ if (i < 8)
+ bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_EOICR,
+ 1);
+ }
+
+ bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SPU, 32);
+ /* No debug. */
+ bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_DCR, 0);
+ /* Disable and clear all interrupts. */
+ bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 0xffffffff);
+ bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_ICCR, 0xffffffff);
+
+ /* Disable all interrupts for DBGU */
+ bus_space_write_4(sc->sc_st, sc->sc_dbg_sh, 0x0c, 0xffffffff);
+
+ if (bus_space_subregion(sc->sc_st, sc->sc_sh,
+ AT91SAM9260_MATRIX_BASE, AT91SAM9260_MATRIX_SIZE,
+ &sc->sc_matrix_sh) != 0)
+ panic("Enable to map matrix registers");
+
+ /* activate NAND*/
+ i = bus_space_read_4(sc->sc_st, sc->sc_matrix_sh,
+ AT91SAM9260_EBICSA);
+ bus_space_write_4(sc->sc_st, sc->sc_matrix_sh,
+ AT91SAM9260_EBICSA,
+ i | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+
+
+ /* Update USB device port clock info */
+ clk = at91_pmc_clock_ref("udpck");
+ clk->pmc_mask = PMC_SCER_UDP_SAM9;
+ at91_pmc_clock_deref(clk);
+
+ /* Update USB host port clock info */
+ clk = at91_pmc_clock_ref("uhpck");
+ clk->pmc_mask = PMC_SCER_UHP_SAM9;
+ at91_pmc_clock_deref(clk);
+
+ /* Each SOC has different PLL contraints */
+ clk = at91_pmc_clock_ref("plla");
+ clk->pll_min_in = SAM9260_PLL_A_MIN_IN_FREQ; /* 1 MHz */
+ clk->pll_max_in = SAM9260_PLL_A_MAX_IN_FREQ; /* 32 MHz */
+ clk->pll_min_out = SAM9260_PLL_A_MIN_OUT_FREQ; /* 80 MHz */
+ clk->pll_max_out = SAM9260_PLL_A_MAX_OUT_FREQ; /* 240 MHz */
+ clk->pll_mul_shift = SAM9260_PLL_A_MUL_SHIFT;
+ clk->pll_mul_mask = SAM9260_PLL_A_MUL_MASK;
+ clk->pll_div_shift = SAM9260_PLL_A_DIV_SHIFT;
+ clk->pll_div_mask = SAM9260_PLL_A_DIV_MASK;
+ clk->set_outb = at91_pll_outa;
+ at91_pmc_clock_deref(clk);
+
+ /*
+ * Fudge MAX pll in frequence down below 3.0 Mhz to ensure
+ * PMC alogrithm choose the divisor that causes the input clock
+ * to be near the optimal 2 Mhz per datasheet. We know
+ * we are going to be using this for the USB clock at 96 Mhz.
+ * Causes no extra frequency deviation for all recomended crystal values.
+ */
+ clk = at91_pmc_clock_ref("pllb");
+ clk->pll_min_in = SAM9260_PLL_B_MIN_IN_FREQ; /* 1 MHz */
+ clk->pll_max_in = SAM9260_PLL_B_MAX_IN_FREQ; /* 5 MHz */
+ clk->pll_max_in = 2999999; /* ~3 MHz */
+ clk->pll_min_out = SAM9260_PLL_B_MIN_OUT_FREQ; /* 70 MHz */
+ clk->pll_max_out = SAM9260_PLL_B_MAX_OUT_FREQ; /* 130 MHz */
+ clk->pll_mul_shift = SAM9260_PLL_B_MUL_SHIFT;
+ clk->pll_mul_mask = SAM9260_PLL_B_MUL_MASK;
+ clk->pll_div_shift = SAM9260_PLL_B_DIV_SHIFT;
+ clk->pll_div_mask = SAM9260_PLL_B_DIV_MASK;
+ clk->set_outb = at91_pll_outb;
+ at91_pmc_clock_deref(clk);
+ return (0);
+}
+
+static device_method_t at91sam9260_methods[] = {
+ DEVMETHOD(device_probe, at91_probe),
+ DEVMETHOD(device_attach, at91_attach),
+ DEVMETHOD(device_identify, at91_identify),
+ {0, 0},
+};
+
+static driver_t at91sam9260_driver = {
+ "at91sam9260",
+ at91sam9260_methods,
+ sizeof(struct at91sam9_softc),
+};
+
+static devclass_t at91sam9260_devclass;
+
+DRIVER_MODULE(at91sam9260, atmelarm, at91sam9260_driver, at91sam9260_devclass, 0, 0);
Added: head/sys/arm/at91/at91sam9260reg.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/at91/at91sam9260reg.h Wed Oct 6 22:40:27 2010 (r213498)
@@ -0,0 +1,310 @@
+/*-
+ * Copyright (c) 2010 Greg Ansley. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* $FreeBSD$ */
+
+#ifndef AT91SAM9260REG_H_
+#define AT91SAM9260REG_H_
+
+#ifndef AT91SAM9260_MASTER_CLOCK
+#define AT91SAM9260_MASTER_CLOCK ((18432000 * 43)/6)
+#endif
+
+/* Chip Specific limits */
+#define SAM9260_PLL_A_MIN_IN_FREQ 1000000 /* 1 Mhz */
+#define SAM9260_PLL_A_MAX_IN_FREQ 32000000 /* 32 Mhz */
+#define SAM9260_PLL_A_MIN_OUT_FREQ 80000000 /* 80 Mhz */
+#define SAM9260_PLL_A_MAX_OUT_FREQ 240000000 /* 240 Mhz */
+#define SAM9260_PLL_A_MUL_SHIFT 16
+#define SAM9260_PLL_A_MUL_MASK 0x3FF
+#define SAM9260_PLL_A_DIV_SHIFT 0
+#define SAM9260_PLL_A_DIV_MASK 0xFF
+
+#define SAM9260_PLL_B_MIN_IN_FREQ 1000000 /* 1 Mhz */
+#define SAM9260_PLL_B_MAX_IN_FREQ 5000000 /* 5 Mhz */
+#define SAM9260_PLL_B_MIN_OUT_FREQ 70000000 /* 70 Mhz */
+#define SAM9260_PLL_B_MAX_OUT_FREQ 130000000 /* 130 Mhz */
+#define SAM9260_PLL_B_MUL_SHIFT 16
+#define SAM9260_PLL_B_MUL_MASK 0x3FF
+#define SAM9260_PLL_B_DIV_SHIFT 0
+#define SAM9260_PLL_B_DIV_MASK 0xFF
+
+/*
+ * Memory map, from datasheet :
+ * 0x00000000 - 0x0ffffffff : Internal Memories
+ * 0x10000000 - 0x1ffffffff : Chip Select 0
+ * 0x20000000 - 0x2ffffffff : Chip Select 1
+ * 0x30000000 - 0x3ffffffff : Chip Select 2
+ * 0x40000000 - 0x4ffffffff : Chip Select 3
+ * 0x50000000 - 0x5ffffffff : Chip Select 4
+ * 0x60000000 - 0x6ffffffff : Chip Select 5
+ * 0x70000000 - 0x7ffffffff : Chip Select 6
+ * 0x80000000 - 0x8ffffffff : Chip Select 7
+ * 0x90000000 - 0xeffffffff : Undefined (Abort)
+ * 0xf0000000 - 0xfffffffff : Peripherals
+ */
+
+#define AT91_CHIPSELECT_0 0x10000000
+#define AT91_CHIPSELECT_1 0x20000000
+#define AT91_CHIPSELECT_2 0x30000000
+#define AT91_CHIPSELECT_3 0x40000000
+#define AT91_CHIPSELECT_4 0x50000000
+#define AT91_CHIPSELECT_5 0x60000000
+#define AT91_CHIPSELECT_6 0x70000000
+#define AT91_CHIPSELECT_7 0x80000000
+
+
+#define AT91SAM9260_BASE 0xd0000000
+
+
+#define AT91SAM9260_EMAC_BASE 0xffc4000
+#define AT91SAM9260_EMAC_SIZE 0x4000
+
+#define AT91SAM9260_RSTC_BASE 0xffffd00
+#define AT91SAM9260_RSTC_SIZE 0x10
+
+#define RSTC_CR 0
+#define RSTC_PROCRST (1 << 0)
+#define RSTC_PERRST (1 << 2)
+#define RSTC_KEY (0xa5 << 24)
+
+/* USART*/
+
+#define AT91SAM9260_USART_SIZE 0x4000
+#define AT91SAM9260_USART0_BASE 0xffb0000
+#define AT91SAM9260_USART0_PDC 0xffb0100
+#define AT91SAM9260_USART0_SIZE AT91SAM9260_USART_SIZE
+#define AT91SAM9260_USART1_BASE 0xffb4000
+#define AT91SAM9260_USART1_PDC 0xffb4100
+#define AT91SAM9260_USART1_SIZE AT91SAM9260_USART_SIZE
+#define AT91SAM9260_USART2_BASE 0xffb8000
+#define AT91SAM9260_USART2_PDC 0xffb8100
+#define AT91SAM9260_USART2_SIZE AT91SAM9260_USART_SIZE
+#define AT91SAM9260_USART3_BASE 0xffd0000
+#define AT91SAM9260_USART3_PDC 0xffd0100
+#define AT91SAM9260_USART3_SIZE AT91SAM9260_USART_SIZE
+#define AT91SAM9260_USART4_BASE 0xffd4000
+#define AT91SAM9260_USART4_PDC 0xffd4100
+#define AT91SAM9260_USART4_SIZE AT91SAM9260_USART_SIZE
+#define AT91SAM9260_USART5_BASE 0xffd8000
+#define AT91SAM9260_USART5_PDC 0xffd8100
+#define AT91SAM9260_USART5_SIZE AT91SAM9260_USART_SIZE
+
+/*TC*/
+#define AT91SAM9260_TC0_BASE 0xffa0000
+#define AT91SAM9260_TC0_SIZE 0x4000
+#define AT91SAM9260_TC0C0_BASE 0xffa0000
+#define AT91SAM9260_TC0C1_BASE 0xffa0040
+#define AT91SAM9260_TC0C2_BASE 0xffa0080
+
+#define AT91SAM9260_TC1_BASE 0xffdc000
+#define AT91SAM9260_TC1_SIZE 0x4000
+
+/*SPI*/
+
+#define AT91SAM9260_SPI0_BASE 0xffc8000
+
+#define AT91SAM9260_SPI0_SIZE 0x4000
+#define AT91SAM9260_IRQ_SPI0 12
+
+#define AT91SAM9260_SPI1_BASE 0xffcc000
+#define AT91SAM9260_SPI1_SIZE 0x4000
+#define AT91SAM9260_IRQ_SPI1 13
+
+/* System Registers */
+#define AT91SAM9260_SYS_BASE 0xffff000
+#define AT91SAM9260_SYS_SIZE 0x1000
+
+#define AT91SAM9260_MATRIX_BASE 0xfffee00
+#define AT91SAM9260_MATRIX_SIZE 0x1000
+#define AT91SAM9260_EBICSA 0x011C
+
+#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
+
+#define AT91SAM9260_DBGU_BASE 0xffff200
+#define AT91SAM9260_DBGU_SIZE 0x200
+
+/*
+ * PIO
+ */
+#define AT91SAM9260_PIOA_BASE 0xffff400
+#define AT91SAM9260_PIOA_SIZE 0x200
+#define AT91SAM9260_PIOB_BASE 0xffff600
+#define AT91SAM9260_PIOB_SIZE 0x200
+#define AT91SAM9260_PIOC_BASE 0xffff800
+#define AT91SAM9260_PIOC_SIZE 0x200
+
+#define AT91RM92_PMC_BASE 0xffffc00
+#define AT91RM92_PMC_SIZE 0x100
+/* IRQs : */
+/*
+ * 0: AIC
+ * 1: System peripheral (System timer, RTC, DBGU)
+ * 2: PIO Controller A
+ * 3: PIO Controller B
+ * 4: PIO Controller C
+ * 5: ADC
+ * 6: USART 0
+ * 7: USART 1
+ * 8: USART 2
+ * 9: MMC Interface
+ * 10: USB device port
+ * 11: Two-wirte interface
+ * 12: SPI 0
+ * 13: SPI 1
+ * 14: SSC
+ * 15: - (reserved)
+ * 16: - (reserved)
+ * 17: Timer Counter 0
+ * 18: Timer Counter 1
+ * 19: Timer Counter 2
+ * 20: USB Host port
+ * 21: EMAC
+ * 22: ISI
+ * 23: USART 3
+ * 24: USART 4
+ * 25: USART 2
+ * 26: Timer Counter 3
+ * 27: Timer Counter 4
+ * 28: Timer Counter 5
+ * 29: AIC IRQ0
+ * 30: AIC IRQ1
+ * 31: AIC IRQ2
+ */
+
+#define AT91SAM9260_IRQ_SYSTEM 1
+#define AT91SAM9260_IRQ_PIOA 2
+#define AT91SAM9260_IRQ_PIOB 3
+#define AT91SAM9260_IRQ_PIOC 4
+#define AT91SAM9260_IRQ_USART0 6
+#define AT91SAM9260_IRQ_USART1 7
+#define AT91SAM9260_IRQ_USART2 8
+#define AT91SAM9260_IRQ_MCI 9
+#define AT91SAM9260_IRQ_UDP 10
+#define AT91SAM9260_IRQ_TWI 11
+#define AT91SAM9260_IRQ_SPI0 12
+#define AT91SAM9260_IRQ_SPI1 13
+#define AT91SAM9260_IRQ_SSC0 14
+#define AT91SAM9260_IRQ_SSC1 15
+#define AT91SAM9260_IRQ_SSC2 16
+#define AT91SAM9260_IRQ_TC0 17
+#define AT91SAM9260_IRQ_TC1 18
+#define AT91SAM9260_IRQ_TC2 19
+#define AT91SAM9260_IRQ_UHP 20
+#define AT91SAM9260_IRQ_EMAC 21
+#define AT91SAM9260_IRQ_USART3 23
+#define AT91SAM9260_IRQ_USART4 24
+#define AT91SAM9260_IRQ_USART5 25
+#define AT91SAM9260_IRQ_AICBASE 29
+
+/* Alias */
+#define AT91SAM9260_IRQ_DBGU AT91SAM9260_IRQ_SYSTEM
+#define AT91SAM9260_IRQ_PMC AT91SAM9260_IRQ_SYSTEM
+#define AT91SAM9260_IRQ_WDT AT91SAM9260_IRQ_SYSTEM
+#define AT91SAM9260_IRQ_PIT AT91SAM9260_IRQ_SYSTEM
+#define AT91SAM9260_IRQ_RSTC AT91SAM9260_IRQ_SYSTEM
+#define AT91SAM9260_IRQ_OHCI AT91SAM9260_IRQ_UHP
+#define AT91SAM9260_IRQ_NAND (-1)
+
+#define AT91SAM9260_AIC_BASE 0xffff000
+#define AT91SAM9260_AIC_SIZE 0x200
+
+/* Timer */
+
+#define AT91SAM9260_WDT_BASE 0xffffd40
+#define AT91SAM9260_WDT_SIZE 0x10
+
+#define AT91SAM9260_PIT_BASE 0xffffd30
+#define AT91SAM9260_PIT_SIZE 10
+
+#define AT91SAM9260_SMC_BASE 0xfffec00
+#define AT91SAM9260_SMC_SIZE 0x200
+
+#define AT91SAM9260_PMC_BASE 0xffffc00
+#define AT91SAM9260_PMC_SIZE 0x100
+
+#define AT91SAM9260_UDP_BASE 0xffa4000
+#define AT91SAM9260_UDP_SIZE 0x4000
+
+#define AT91SAM9260_MCI_BASE 0xffa8000
+#define AT91SAM9260_MCI_SIZE 0x4000
+
+#define AT91SAM9260_TWI_BASE 0xffaC000
+#define AT91SAM9260_TWI_SIZE 0x4000
+
+/* XXX Needs to be carfully coordinated with
+ * other * soc's so phyical and vm address
+ * mapping are unique. XXX
+ */
+#define AT91SAM9260_OHCI_BASE 0xdfc00000
+#define AT91SAM9260_OHCI_PA_BASE 0x00500000
+#define AT91SAM9260_OHCI_SIZE 0x00100000
+
+#define AT91SAM9260_NAND_BASE 0xe0000000
+#define AT91SAM9260_NAND_PA_BASE 0x40000000
+#define AT91SAM9260_NAND_SIZE 0x10000000
+
+
+/* SDRAMC */
+#define AT91SAM9260_SDRAMC_BASE 0xfffea00
+#define AT91SAM9260_SDRAMC_MR 0x00
+#define AT91SAM9260_SDRAMC_MR_MODE_NORMAL 0
+#define AT91SAM9260_SDRAMC_MR_MODE_NOP 1
+#define AT91SAM9260_SDRAMC_MR_MODE_PRECHARGE 2
+#define AT91SAM9260_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3
+#define AT91SAM9260_SDRAMC_MR_MODE_REFRESH 4
+#define AT91SAM9260_SDRAMC_TR 0x04
+#define AT91SAM9260_SDRAMC_CR 0x08
+#define AT91SAM9260_SDRAMC_CR_NC_8 0x0
+#define AT91SAM9260_SDRAMC_CR_NC_9 0x1
+#define AT91SAM9260_SDRAMC_CR_NC_10 0x2
+#define AT91SAM9260_SDRAMC_CR_NC_11 0x3
+#define AT91SAM9260_SDRAMC_CR_NC_MASK 0x00000003
+#define AT91SAM9260_SDRAMC_CR_NR_11 0x0
+#define AT91SAM9260_SDRAMC_CR_NR_12 0x4
+#define AT91SAM9260_SDRAMC_CR_NR_13 0x8
+#define AT91SAM9260_SDRAMC_CR_NR_RES 0xc
+#define AT91SAM9260_SDRAMC_CR_NR_MASK 0x0000000c
+#define AT91SAM9260_SDRAMC_CR_NB_2 0x00
+#define AT91SAM9260_SDRAMC_CR_NB_4 0x10
+#define AT91SAM9260_SDRAMC_CR_DBW_16 0x80
+#define AT91SAM9260_SDRAMC_CR_NB_MASK 0x00000010
+#define AT91SAM9260_SDRAMC_CR_NCAS_MASK 0x00000060
+#define AT91SAM9260_SDRAMC_CR_TWR_MASK 0x00000780
+#define AT91SAM9260_SDRAMC_CR_TRC_MASK 0x00007800
+#define AT91SAM9260_SDRAMC_CR_TRP_MASK 0x00078000
+#define AT91SAM9260_SDRAMC_CR_TRCD_MASK 0x00780000
+#define AT91SAM9260_SDRAMC_CR_TRAS_MASK 0x07800000
+#define AT91SAM9260_SDRAMC_CR_TXSR_MASK 0x78000000
+#define AT91SAM9260_SDRAMC_HSR 0x0c
+#define AT91SAM9260_SDRAMC_LPR 0x10
+#define AT91SAM9260_SDRAMC_IER 0x14
+#define AT91SAM9260_SDRAMC_IDR 0x18
+#define AT91SAM9260_SDRAMC_IMR 0x1c
+#define AT91SAM9260_SDRAMC_ISR 0x20
+#define AT91SAM9260_SDRAMC_MDR 0x24
+
+#endif /* AT91SAM9260REG_H_*/
+
Modified: head/sys/arm/at91/at91sam9g20.c
==============================================================================
--- head/sys/arm/at91/at91sam9g20.c Wed Oct 6 22:32:31 2010 (r213497)
+++ head/sys/arm/at91/at91sam9g20.c Wed Oct 6 22:40:27 2010 (r213498)
@@ -176,6 +176,30 @@ at91_cpu_add_builtin_children(device_t d
}
}
+static uint32_t
+at91_pll_outa(int freq)
+{
+
+ switch (freq / 10000000) {
+ case 747 ... 801: return ((1 << 29) | (0 << 14));
+ case 697 ... 746: return ((1 << 29) | (1 << 14));
+ case 647 ... 696: return ((1 << 29) | (2 << 14));
+ case 597 ... 646: return ((1 << 29) | (3 << 14));
+ case 547 ... 596: return ((1 << 29) | (1 << 14));
+ case 497 ... 546: return ((1 << 29) | (2 << 14));
+ case 447 ... 496: return ((1 << 29) | (3 << 14));
+ case 397 ... 446: return ((1 << 29) | (4 << 14));
+ default: return (1 << 29);
+ }
+}
+
+static uint32_t
+at91_pll_outb(int freq)
+{
+
+ return (0);
+}
+
static void
at91_identify(driver_t *drv, device_t parent)
{
@@ -284,6 +308,7 @@ at91_attach(device_t dev)
clk->pll_mul_mask = SAM9G20_PLL_A_MUL_MASK;
clk->pll_div_shift = SAM9G20_PLL_A_DIV_SHIFT;
clk->pll_div_mask = SAM9G20_PLL_A_DIV_MASK;
+ clk->set_outb = at91_pll_outa;
at91_pmc_clock_deref(clk);
clk = at91_pmc_clock_ref("pllb");
@@ -295,6 +320,7 @@ at91_attach(device_t dev)
clk->pll_mul_mask = SAM9G20_PLL_B_MUL_MASK;
clk->pll_div_shift = SAM9G20_PLL_B_DIV_SHIFT;
clk->pll_div_mask = SAM9G20_PLL_B_DIV_MASK;
+ clk->set_outb = at91_pll_outb;
at91_pmc_clock_deref(clk);
return (0);
}
Added: head/sys/arm/at91/board_qila9g20.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/at91/board_qila9g20.c Wed Oct 6 22:40:27 2010 (r213498)
@@ -0,0 +1,105 @@
+/*-
+ * Copyright (c) 2009 Greg Ansley. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* Calao Systems QIL-9G20-Cxx
+ * http://www.calao-systems.com
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <arm/at91/at91board.h>
+#include <arm/at91/at91reg.h>
+#include <arm/at91/at91var.h>
+#include <arm/at91/at91sam9g20reg.h>
+#include <arm/at91/at91_piovar.h>
+#include <arm/at91/at91_pio_sam9g20.h>
+//#include <arm/at91/at91_led.h>
+
+#define AT91SAM9G20_LED_BASE AT91SAM9G20_PIOA_BASE
+#define AT91SAM9G20_LED_SIZE AT91SAM9G20_PIO_SIZE
+#define AT91SAM9G20_IRQ_LED AT91SAM9G20_IRQ_PIOA
+
+long
+board_init(void)
+{
+
+ //at91_led_create("power", 0, 9, 0);
+
+ /* PIOB's A periph: Turn USART 0's TX/RX pins */
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB14_DRXD, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB15_DTXD, 1);
+
+ /* PIOB's A periph: Turn USART 0's TX/RX pins */
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB4_TXD0, 1);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB5_RXD0, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB22_DSR0, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB23_DCD0, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB24_DTR0, 1);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB25_RI0, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB26_RTS0, 1);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB27_CTS0, 0);
+
+ /* PIOB's A periph: Turn USART 1's TX/RX pins */
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB6_TXD1, 1);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB7_RXD1, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB28_RTS1, 1);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB29_CTS1, 0);
+
+ /* TWI Two-wire Serial Data */
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA23_TWD, 1);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA24_TWCK, 1);
+
+ /* Multimedia Card */
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA6_MCDA0, 1);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA7_MCCDA, 1);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA8_MCCK, 1);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA9_MCDA1, 1);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA10_MCDA2, 1);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA11_MCDA3, 1);
+
+ /* SPI0 to DataFlash */
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PA0_SPI0_MISO, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PA1_SPI0_MOSI, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PA2_SPI0_SPCK, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PA3_SPI0_NPCS0, 0);
+
+ /* EMAC */
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA19_ETXCK, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA21_EMDIO, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA20_EMDC, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA17_ERXDV, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA16_ETXEN, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA12_ETX0 , 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA13_ETX1, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA14_ERX0, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA15_ERX1, 0);
+ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA18_ERXER, 0);
+
+
+ return (at91_ramsize());
+}
Modified: head/sys/arm/at91/board_sam9g20ek.c
==============================================================================
--- head/sys/arm/at91/board_sam9g20ek.c Wed Oct 6 22:32:31 2010 (r213497)
+++ head/sys/arm/at91/board_sam9g20ek.c Wed Oct 6 22:40:27 2010 (r213498)
@@ -23,7 +23,14 @@
* SUCH DAMAGE.
*/
-/* Atmel AT91SAM9G20EK Rev. B Development Card */
+/*
+ * This board file can be used for both:
+ * Atmel AT91SAM9260-B Development Card and
+ * Atmel AT91SAM9G20-EK Rev. B Development Card
+ *
+ * Since the AT91SAM9260 and AT91SAM9G20 have identical memory maps and
+ * pin configurations we can use the same file for both.
+ */
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
@@ -38,16 +45,9 @@ __FBSDID("$FreeBSD$");
#include <arm/at91/at91_pio_sam9g20.h>
//#include <arm/at91/at91_led.h>
-#define AT91SAM9G20_LED_BASE AT91SAM9G20_PIOA_BASE
-#define AT91SAM9G20_LED_SIZE AT91SAM9G20_PIO_SIZE
-#define AT91SAM9G20_IRQ_LED AT91SAM9G20_IRQ_PIOA
-
long
board_init(void)
{
-
- //at91_led_create("power", 0, 9, 0);
-
/* PIOB's A periph: Turn USART 0's TX/RX pins */
at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB14_DRXD, 0);
at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB15_DTXD, 1);
@@ -68,16 +68,13 @@ board_init(void)
at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB28_RTS1, 1);
at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB29_CTS1, 0);
-#if 1
/* TWI Two-wire Serial Data */
at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA23_TWD, 1);
at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA24_TWCK, 1);
-#endif
+
#if 1
/*
* Turn off Clock to DataFlash, conflicts with MCI clock.
- * Remove resistor R42 if you need both DataFlash and SD Card
- * access at the same time
*/
at91_pio_use_gpio(AT91SAM9G20_PIOA_BASE,AT91C_PIO_PA2);
at91_pio_gpio_input(AT91SAM9G20_PIOA_BASE,AT91C_PIO_PA2);
@@ -106,45 +103,6 @@ board_init(void)
at91_pio_use_gpio(AT91SAM9G20_PIOA_BASE,AT91C_PIO_PA8);
#endif
-#if 0
- static int at91_base = AT91SAM9G20_BASE;
- volatile uint32_t *PIO = (uint32_t *)(at91_base + AT91SAM9G20_PIOA_BASE);
- volatile uint32_t *RST = (uint32_t *)(at91_base + AT91SAM9G20_RSTC_BASE);
- /*
- * Disable pull-up on:
- * ERX0 (PA14) => PHY ADDR0
- * ERX1 (PA15) => PHY ADDR1
- * RXDV (PA17) => PHY normal mode (not Test mode)
- * ERX2 (PA25) => PHY ADDR2
- * ERX3 (PA26) => PHY ADDR3
- * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
- *
- * PHY has internal pull-down
- */
- PIO[PIO_PUDR/4] =
- AT91C_PA14_ERX0 |
- AT91C_PA15_ERX1 |
- AT91C_PA17_ERXDV |
- AT91C_PA25_ERX2 |
- AT91C_PA26_ERX3 |
- AT91C_PA28_ECRS;
-
-
- /* Reset PHY - 500ms */
- RST[2] = 0xA5000D01;
- RST[0] = 0xA5000080;
- while (!(RST[1] & (1 << 16))) ;
-
- PIO[PIO_PUER/4] =
- AT91C_PA14_ERX0 |
- AT91C_PA15_ERX1 |
- AT91C_PA17_ERXDV |
- AT91C_PA25_ERX2 |
- AT91C_PA26_ERX3 |
- AT91C_PA28_ECRS;
-#endif
-
-
/* EMAC */
at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA12_ETX0 , 0);
at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA13_ETX1, 0);
@@ -166,11 +124,5 @@ board_init(void)
at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA28_ECRS, 0);
at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA29_ECOL, 0);
-#if 0
- /* Handle Missing ETXER line */
- at91_pio_use_gpio(AT91SAM9G20_PIOA_BASE,AT91C_PA22_ETXER);
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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