svn commit: r202732 - head/sys/mips/mips

[Neel Natu]

Author: neel
Date: Thu Jan 21 02:21:31 2010
New Revision: 202732
URL: http://svn.freebsd.org/changeset/base/202732

Log:
  Get rid of redundant setting of interrupt enable bit when restoring the status
  register from the PCB.
  
  Remove a couple of misleading comments while I am here. The comments are
  misleading because they imply that interrupts will be enabled after the
  status register is restored from the PCB. This is not the case because
  the processor is at the exception level (SR_EXL is set).
  
  Approved by: imp (mentor)

Modified:
  head/sys/mips/mips/exception.S

Modified: head/sys/mips/mips/exception.S
==============================================================================
--- head/sys/mips/mips/exception.S	Thu Jan 21 00:54:22 2010	(r202731)
+++ head/sys/mips/mips/exception.S	Thu Jan 21 02:21:31 2010	(r202732)
@@ -581,16 +581,10 @@ NNON_LEAF(MipsUserGenException, STAND_FR
 #ifdef TARGET_OCTEON
 	and k0, k0, ~(MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX)
 #endif
-	or  k0, k0, (MIPS_SR_INT_IE)
 	.set noat
 	RESTORE_U_PCB_REG(AT, AST, k1)
 
-/*
- * The restoration of the user SR must be done only after
- * k1 is no longer needed.  Otherwise, k1 will get clobbered after
- * interrupts are enabled.
- */
-	mtc0	k0, COP_0_STATUS_REG	# still exeption level
+	mtc0	k0, COP_0_STATUS_REG	# still exception level
 	ITLBNOPFIX
 	sync
 	eret
@@ -814,15 +808,9 @@ NNON_LEAF(MipsUserIntr, STAND_FRAME_SIZE
 #ifdef TARGET_OCTEON
 	and k0, k0, ~(MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX)
 #endif
-	or  k0, k0, (MIPS_SR_INT_IE|SR_EXL)
 	.set	noat
 	RESTORE_U_PCB_REG(AT, AST, k1)
 
-/*
- * The restoration of the user SR must be done only after
- * k1 is no longer needed.  Otherwise, k1 will get clobbered after
- * interrupts are enabled.
- */
 	mtc0	k0, COP_0_STATUS_REG	# SR with EXL set. 
 	ITLBNOPFIX
 	sync