svn commit: r210986 - in head/sys/mips: include mips

[Neel Natu]

Author: neel
Date: Sat Aug  7 01:49:44 2010
New Revision: 210986
URL: http://svn.freebsd.org/changeset/base/210986

Log:
  - Consolidate the the cache coherence attribute definitions in a single place.
    Adapted from Juli's changes to pte.h in the octeon branch:
    http://svn.freebsd.org/viewvc/base/user/jmallett/octeon/sys/mips/include/pte.h
  
  - Set the KX and UX bits in the status register for n64 kernels.
  
  Reviewed by:	jmallett

Modified:
  head/sys/mips/include/cpuregs.h
  head/sys/mips/include/pte.h
  head/sys/mips/mips/locore.S
  head/sys/mips/mips/mpboot.S

Modified: head/sys/mips/include/cpuregs.h
==============================================================================
--- head/sys/mips/include/cpuregs.h	Sat Aug  7 01:05:02 2010	(r210985)
+++ head/sys/mips/include/cpuregs.h	Sat Aug  7 01:49:44 2010	(r210986)
@@ -110,15 +110,75 @@
 #define	MIPS_XKPHYS_START		0x8000000000000000
 #define	MIPS_XKPHYS_END			0xbfffffffffffffff
 
-#define	MIPS_CCA_UC		0x02	/* Uncached.  */
-#define	MIPS_CCA_CNC		0x03	/* Cacheable non-coherent.  */
+/*
+ * Cache Coherency Attributes:
+ *	UC:	Uncached.
+ *	UA:	Uncached accelerated.
+ *	C:	Cacheable, coherency unspecified.
+ *	CNC:	Cacheable non-coherent.
+ *	CC:	Cacheable coherent.
+ *	CCE:	Cacheable coherent, exclusive read.
+ *	CCEW:	Cacheable coherent, exclusive write.
+ *	CCUOW:	Cacheable coherent, update on write.
+ *
+ * Note that some bits vary in meaning across implementations (and that the
+ * listing here is no doubt incomplete) and that the optimal cached mode varies
+ * between implementations.  0x02 is required to be UC and 0x03 is required to
+ * be a least C.
+ *
+ * We define the following logical bits:
+ * 	UNCACHED:
+ * 		The optimal uncached mode for the target CPU type.  This must
+ * 		be suitable for use in accessing memory-mapped devices.
+ * 	CACHED:	The optional cached mode for the target CPU type.
+ */
+
+#define	MIPS_CCA_UC		0x02	/* Uncached. */
+#define	MIPS_CCA_C		0x03	/* Cacheable, coherency unspecified. */
+
+#if defined(CPU_R4000) || defined(CPU_R10000)
+#define	MIPS_CCA_CNC	0x03
+#define	MIPS_CCA_CCE	0x04
+#define	MIPS_CCA_CCEW	0x05
+
+#ifdef CPU_R4000
+#define	MIPS_CCA_CCUOW	0x06
+#endif
+
+#ifdef CPU_R10000
+#define	MIPS_CCA_UA	0x07
+#endif
+
+#define	MIPS_CCA_CACHED	MIPS_CCA_CCEW
+#endif /* defined(CPU_R4000) || defined(CPU_R10000) */
+
+#if defined(CPU_SB1)
+#define	MIPS_CCA_CC	0x05	/* Cacheable Coherent. */
+#endif
+
+#ifndef	MIPS_CCA_UNCACHED
+#define	MIPS_CCA_UNCACHED	MIPS_CCA_UC
+#endif
+
+/*
+ * If we don't know which cached mode to use and there is a cache coherent
+ * mode, use it.  If there is not a cache coherent mode, use the required
+ * cacheable mode.
+ */
+#ifndef MIPS_CCA_CACHED
+#ifdef MIPS_CCA_CC
+#define	MIPS_CCA_CACHED	MIPS_CCA_CC
+#else
+#define	MIPS_CCA_CACHED	MIPS_CCA_C
+#endif
+#endif
 
 #define	MIPS_PHYS_TO_XKPHYS(cca,x) \
 	((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
 #define	MIPS_PHYS_TO_XKPHYS_CACHED(x) \
-	((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_CNC) << 59) | (x))
+	((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_CACHED) << 59) | (x))
 #define	MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \
-	((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_UC) << 59) | (x))
+	((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_UNCACHED) << 59) | (x))
 
 #define	MIPS_XKPHYS_TO_PHYS(x)		((x) & 0x07ffffffffffffffULL)
 

Modified: head/sys/mips/include/pte.h
==============================================================================
--- head/sys/mips/include/pte.h	Sat Aug  7 01:05:02 2010	(r210985)
+++ head/sys/mips/include/pte.h	Sat Aug  7 01:49:44 2010	(r210986)
@@ -113,17 +113,8 @@ typedef	pt_entry_t *pd_entry_t;
  * 		it is matched.
  */
 #define	PTE_C(attr)	((attr & 0x07) << 3)
-#define	PTE_C_UNCACHED	(PTE_C(0x02))
-/*
- * The preferred cache attribute for cacheable pages, this can be 
- * implementation dependent. We will use the standard value 0x3 as 
- * default.
- */
-#if defined(CPU_SB1)
-#define	PTE_C_CACHE	(PTE_C(0x05))
-#else
-#define	PTE_C_CACHE	(PTE_C(0x03))
-#endif
+#define	PTE_C_UNCACHED	(PTE_C(MIPS_CCA_UNCACHED))
+#define	PTE_C_CACHE	(PTE_C(MIPS_CCA_CACHED))
 #define	PTE_D		0x04
 #define	PTE_V		0x02
 #define	PTE_G		0x01

Modified: head/sys/mips/mips/locore.S
==============================================================================
--- head/sys/mips/mips/locore.S	Sat Aug  7 01:05:02 2010	(r210985)
+++ head/sys/mips/mips/locore.S	Sat Aug  7 01:49:44 2010	(r210986)
@@ -117,6 +117,9 @@ VECTOR(_locore, unknown)
 	 *	Enable FPU
 	 */
 	li	t1, MIPS_SR_COP_1_BIT
+#ifdef __mips_n64
+	or	t1, MIPS_SR_KX | MIPS_SR_UX
+#endif
 #endif
 	/*
 	 * Read coprocessor 0 status register, clear bits not
@@ -130,7 +133,7 @@ VECTOR(_locore, unknown)
 	COP0_SYNC
 
 	/* Make sure KSEG0 is cached */
-	li	t0, MIPS_CCA_CNC
+	li	t0, MIPS_CCA_CACHED
 	mtc0	t0, MIPS_COP_0_CONFIG
 	COP0_SYNC
 

Modified: head/sys/mips/mips/mpboot.S
==============================================================================
--- head/sys/mips/mips/mpboot.S	Sat Aug  7 01:05:02 2010	(r210985)
+++ head/sys/mips/mips/mpboot.S	Sat Aug  7 01:49:44 2010	(r210986)
@@ -54,7 +54,7 @@ GLOBAL(mpentry)
 
 	mtc0	zero, MIPS_COP_0_CAUSE	/* clear soft interrupts */
 
-	li	t0, MIPS_CCA_CNC	/* make sure kseg0 is cached */
+	li	t0, MIPS_CCA_CACHED	/* make sure kseg0 is cached */
 	mtc0	t0, MIPS_COP_0_CONFIG
 	COP0_SYNC