svn commit: r186352 - in head/sys: . arm/arm arm/conf arm/include
arm/xscale/ixp425 boot/arm/ixp425/boot2 conf contrib/dev/npe
Sam Leffler
sam at FreeBSD.org
Sat Dec 20 03:26:10 UTC 2008
Author: sam
Date: Sat Dec 20 03:26:09 2008
New Revision: 186352
URL: http://svn.freebsd.org/changeset/base/186352
Log:
Merge support for Gateworks Cambria boards:
o add support for IXP435 cpu's (e.g. 64 irq's)
o add support for Cambria-specific devices: npe, led's (front panel and
octal latch), ehci, mcu, ide cf
o redo memory mapping for xscale/ixp4xx boards: previously memory
was assumed aliased to 0x10000000 but this appears to be true only
for ixp425 systems and breaks operation on others; rework so memory
is assumed to start at 0
o rework NPE configuration support to use NPE id's instead of port #'s;
these changes also rename the associated MAC's to follow the NPE's
they are attached to
o update npe firmware to latest rev (same license) and update default fw
imageid's to match; in particular this adds NPE-A and crypto support
o re-style NPE fw handling code and add a console msg identifying the
attributes of the loaded fw
o fix numerous problems with handling failures during npe setup
o fix npe rx q setup; need to spin waiting for mailbox responses during
early boot stages as qmgr interrupts are not delivered; this fixes
the problem where all 8 traffic classifications were not tied to the
rx q (and eliminates the console msg "remember to fix rx q setup")
o add DELAY to npe MII wait logic for IXP435
o strip down builtin phys->virt address translation table in resource
handling to just those resources that require it and add a console msg
to alert people when this (kludge) table needs to be extended
o purge a bunch of dead netbsd-ism's
o cleanup avila led driver
o add Cambria support to boot2 and rework code for better multi-board support
Notes:
1. NPE-A doesn't work and causes NPE-C to stop working; it is disabled
in the hints
2. USB isn't working yet; controller communicates ok but device
discovery fails
3. Cambria support must be configured separately from IXP425 boards;
multi-board support is TBD
Sponsored by: Hobnob, Gateworks (board donation)
Reviewed by: imp
Added:
head/sys/arm/conf/CAMBRIA (contents, props changed)
- copied, changed from r186349, projects/cambria/sys/arm/conf/CAMBRIA
head/sys/arm/conf/CAMBRIA.hints (props changed)
- copied unchanged from r186349, projects/cambria/sys/arm/conf/CAMBRIA.hints
head/sys/arm/xscale/ixp425/cambria_fled.c
- copied unchanged from r186349, projects/cambria/sys/arm/xscale/ixp425/cambria_fled.c
head/sys/arm/xscale/ixp425/cambria_led.c
- copied unchanged from r186349, projects/cambria/sys/arm/xscale/ixp425/cambria_led.c
head/sys/arm/xscale/ixp425/ixp435_ehci.c
- copied unchanged from r186349, projects/cambria/sys/arm/xscale/ixp425/ixp435_ehci.c
head/sys/arm/xscale/ixp425/std.ixp435
- copied unchanged from r186349, projects/cambria/sys/arm/xscale/ixp425/std.ixp435
Modified:
head/sys/ (props changed)
head/sys/arm/arm/cpufunc.c
head/sys/arm/arm/identcpu.c
head/sys/arm/conf/AVILA
head/sys/arm/conf/AVILA.hints
head/sys/arm/include/armreg.h
head/sys/arm/include/intr.h
head/sys/arm/xscale/ixp425/avila_ata.c
head/sys/arm/xscale/ixp425/avila_led.c
head/sys/arm/xscale/ixp425/avila_machdep.c
head/sys/arm/xscale/ixp425/files.avila
head/sys/arm/xscale/ixp425/files.ixp425
head/sys/arm/xscale/ixp425/if_npe.c
head/sys/arm/xscale/ixp425/if_npereg.h
head/sys/arm/xscale/ixp425/ixp425.c
head/sys/arm/xscale/ixp425/ixp425_iic.c
head/sys/arm/xscale/ixp425/ixp425_intr.h
head/sys/arm/xscale/ixp425/ixp425_mem.c
head/sys/arm/xscale/ixp425/ixp425_npe.c
head/sys/arm/xscale/ixp425/ixp425_npevar.h
head/sys/arm/xscale/ixp425/ixp425_pci.c
head/sys/arm/xscale/ixp425/ixp425_qmgr.c
head/sys/arm/xscale/ixp425/ixp425_timer.c
head/sys/arm/xscale/ixp425/ixp425_wdog.c
head/sys/arm/xscale/ixp425/ixp425reg.h
head/sys/arm/xscale/ixp425/ixp425var.h
head/sys/arm/xscale/ixp425/std.avila
head/sys/boot/arm/ixp425/boot2/arm_init.S
head/sys/boot/arm/ixp425/boot2/boot2.c
head/sys/boot/arm/ixp425/boot2/ixp425_board.c
head/sys/boot/arm/ixp425/boot2/lib.h
head/sys/conf/options.arm
head/sys/contrib/dev/npe/IxNpeMicrocode.dat.uu
Modified: head/sys/arm/arm/cpufunc.c
==============================================================================
--- head/sys/arm/arm/cpufunc.c Sat Dec 20 03:02:32 2008 (r186351)
+++ head/sys/arm/arm/cpufunc.c Sat Dec 20 03:26:09 2008 (r186352)
@@ -1211,7 +1211,7 @@ set_cpufuncs()
#endif /* CPU_XSCALE_PXA2X0 */
#ifdef CPU_XSCALE_IXP425
if (cputype == CPU_ID_IXP425_533 || cputype == CPU_ID_IXP425_400 ||
- cputype == CPU_ID_IXP425_266) {
+ cputype == CPU_ID_IXP425_266 || cputype == CPU_ID_IXP435) {
cpufuncs = xscale_cpufuncs;
#if defined(PERFCTRS)
Modified: head/sys/arm/arm/identcpu.c
==============================================================================
--- head/sys/arm/arm/identcpu.c Sat Dec 20 03:02:32 2008 (r186351)
+++ head/sys/arm/arm/identcpu.c Sat Dec 20 03:26:09 2008 (r186352)
@@ -300,6 +300,10 @@ const struct cpuidtab cpuids[] = {
{ CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz",
ixp425_steppings },
+ /* XXX ixp435 steppings? */
+ { CPU_ID_IXP435, CPU_CLASS_XSCALE, "IXP435",
+ ixp425_steppings },
+
{ CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S",
generic_steppings },
{ CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S R1",
Modified: head/sys/arm/conf/AVILA
==============================================================================
--- head/sys/arm/conf/AVILA Sat Dec 20 03:02:32 2008 (r186351)
+++ head/sys/arm/conf/AVILA Sat Dec 20 03:26:09 2008 (r186352)
@@ -20,20 +20,18 @@
ident AVILA
-options PHYSADDR=0x10000000
-options KERNPHYSADDR=0x10200000
-options KERNVIRTADDR=0xc0200000 # Used in ldscript.arm
-options FLASHADDR=0x50000000
-options LOADERRAMADDR=0x00000000
-options STARTUP_PAGETABLE_ADDR=0x10000000
-
+include "../xscale/ixp425/std.ixp425"
+# NB: memory mapping is defined in std.avila
include "../xscale/ixp425/std.avila"
+options XSCALE_CACHE_READ_WRITE_ALLOCATE
+#options ARM_USE_SMALL_ALLOC
#To statically compile in device wiring instead of /boot/device.hints
hints "AVILA.hints" #Default places to look for devices.
makeoptions MODULES_OVERRIDE=""
makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
makeoptions CONF_CFLAGS=-mcpu=xscale
+makeoptions MODULES_OVERRIDE=""
#options HZ=1000
options HZ=100
options DEVICE_POLLING
@@ -42,34 +40,18 @@ options DEVICE_POLLING
options KDB
#options GDB
options DDB #Enable the kernel debugger
-#options INVARIANTS #Enable calls of extra sanity checking
-#options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
+options INVARIANTS #Enable calls of extra sanity checking
+options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
#options WITNESS #Enable checks to detect deadlocks and cycles
#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
#options DIAGNOSTIC
options SCHED_4BSD #4BSD scheduler
options INET #InterNETworking
-options INET6 #IPv6 communications protocols
options FFS #Berkeley Fast Filesystem
options SOFTUPDATES #Enable FFS soft updates support
-options UFS_ACL #Support for access control lists
-options UFS_DIRHASH #Improve performance on big directories
options NFSCLIENT #Network Filesystem Client
-options NFSSERVER #Network Filesystem Server
-options NFSLOCKD #Network Lock Manager
options NFS_ROOT #NFS usable as /, requires NFSCLIENT
-#options MSDOSFS #MSDOS Filesystem
-options CD9660 #ISO 9660 Filesystem
-#options PROCFS #Process filesystem (requires PSEUDOFS)
-options PSEUDOFS #Pseudo-filesystem framework
-options SCSI_DELAY=5000 #Delay (in ms) before probing SCSI
-options KTRACE #ktrace(1) support
-options SYSVSHM #SYSV-style shared memory
-options SYSVMSG #SYSV-style message queues
-options SYSVSEM #SYSV-style semaphores
-options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
-options KBD_INSTALL_CDEV # install a CDEV entry in /dev
options BOOTP
options BOOTP_NFSROOT
options BOOTP_NFSV3
@@ -106,7 +88,6 @@ device npe_fw
device firmware
device qmgr # Q Manager (required by npe)
device miibus # NB: required by npe
-device rl # RealTek 8129/8139
device ether
device bpf
@@ -114,37 +95,48 @@ device pty
device loop
device if_bridge
-options XSCALE_CACHE_READ_WRITE_ALLOCATE
device md
device random # Entropy device
-#options ARM_USE_SMALL_ALLOC
-
# Wireless NIC cards
device wlan # 802.11 support
+options IEEE80211_DEBUG
device wlan_wep # 802.11 WEP support
device wlan_ccmp # 802.11 CCMP support
device wlan_tkip # 802.11 TKIP support
device wlan_xauth
+
device ath # Atheros pci/cardbus NIC's
-device ath_hal # Atheros HAL (Hardware Access Layer)
-options AH_SUPPORT_AR5416 # enable AR5416 tx/rx descriptors
-device ath_rate_sample # SampleRate tx rate control for ath
options ATH_DEBUG
+options ATH_DIAGAPI
+#options ATH_TX99_DIAG
+device ath_rate_sample # SampleRate tx rate control for ath
-#device crypto
-#device cryptodev
-#device hifn # NB: Soekris minipci card known to work
+#options AH_DEBUG
+#options AH_ASSERT
+#device ath_ar5210
+#device ath_ar5211
+device ath_ar5212
+device ath_rf2413
+device ath_rf2417
+device ath_rf2425
+device ath_rf5111
+device ath_rf5112
+device ath_rf5413
+#
+device ath_ar5416
+options AH_SUPPORT_AR5416
+device ath_ar9160
device usb
-options USB_DEBUG
+#options USB_DEBUG
device ohci
device ehci
device ugen
-device umass
-device scbus # SCSI bus (required for SCSI)
-device da # Direct Access (disks)
-
-device ural
-device zyd
-device wlan_amrr
+#device umass
+#device scbus # SCSI bus (required for SCSI)
+#device da # Direct Access (disks)
+
+#device ural
+#device zyd
+#device wlan_amrr
Modified: head/sys/arm/conf/AVILA.hints
==============================================================================
--- head/sys/arm/conf/AVILA.hints Sat Dec 20 03:02:32 2008 (r186351)
+++ head/sys/arm/conf/AVILA.hints Sat Dec 20 03:26:09 2008 (r186352)
@@ -17,21 +17,22 @@ hint.uart.1.irq=13
# NPE Hardware Queue Manager
hint.ixpqmgr.0.at="ixp0"
-# NPE wireless NIC's, requires ixpqmgr
+# NPE wired NIC's, requires ixpqmgr
hint.npe.0.at="ixp0"
-hint.npe.0.mac="A"
-hint.npe.0.mii="A"
+hint.npe.0.npeid="B"
+hint.npe.0.mac="B"
+hint.npe.0.mii="B"
hint.npe.0.phy=0
hint.npe.1.at="ixp0"
-hint.npe.1.mac="B"
-# NB: on 2348 boards all PHY's are addressed through MAC A
-hint.npe.1.mii="A"
+hint.npe.1.npeid="C"
+hint.npe.1.mac="C"
+hint.npe.1.mii="B"
hint.npe.1.phy=1
# CF IDE controller
hint.ata_avila.0.at="ixp0"
-# LED connected to gpio
+# Front Panel LED
hint.led_avila.0.at="ixp0"
# Analog Devices AD7418 temperature sensor
Copied and modified: head/sys/arm/conf/CAMBRIA (from r186349, projects/cambria/sys/arm/conf/CAMBRIA)
==============================================================================
--- projects/cambria/sys/arm/conf/CAMBRIA Sat Dec 20 01:29:19 2008 (r186349, copy source)
+++ head/sys/arm/conf/CAMBRIA Sat Dec 20 03:26:09 2008 (r186352)
@@ -101,8 +101,8 @@ device random # Entrop
# NB: 2 USB 2.0 ports standard
device usb
-options USB_DEBUG
-device ohci
+options USB_EHCI_BIG_ENDIAN_DESC # handle big-endian byte order
+#options USB_DEBUG
device ehci
device ugen
device umass
Copied: head/sys/arm/conf/CAMBRIA.hints (from r186349, projects/cambria/sys/arm/conf/CAMBRIA.hints)
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/conf/CAMBRIA.hints Sat Dec 20 03:26:09 2008 (r186352, copy of r186349, projects/cambria/sys/arm/conf/CAMBRIA.hints)
@@ -0,0 +1,54 @@
+# $FreeBSD$
+
+#
+# Device wiring for the Gateworks Cambria 2358.
+#
+
+# DBGU is unit 0
+hint.uart.0.at="ixp0"
+hint.uart.0.addr=0xc8000000
+hint.uart.0.irq=15
+hint.uart.0.flags=0x10
+
+# NB: no UART1 on ixp436
+
+# NPE Hardware Queue Manager
+hint.ixpqmgr.0.at="ixp0"
+
+# NPE wired NIC's, requires ixpqmgr
+hint.npe.0.at="ixp0"
+hint.npe.0.npeid="C"
+hint.npe.0.mac="C"
+hint.npe.0.mii="C"
+hint.npe.0.phy=1
+#hint.npe.1.at="ixp0"
+#hint.npe.1.npeid="A"
+#hint.npe.1.mac="A"
+#hint.npe.1.mii="C"
+#hint.npe.1.phy=2
+
+# CF IDE controller
+hint.ata_avila.0.at="ixp0"
+
+# Front Panel LED
+hint.fled.0.at="iicbus0"
+hint.fled.0.addr=0x5a
+
+# Octal LED Latch
+hint.led_cambria.0.at="ixp0"
+
+# Analog Devices AD7418 temperature sensor
+hint.ad7418.0.at="iicbus0"
+hint.ad7418.0.addr=0x50
+
+# Dallas Semiconductor DS1672 RTC
+hint.ds1672.0.at="iicbus0"
+hint.ds1672.0.addr=0xd0
+
+# USB is part of the chip
+hint.ehci.0.at="ixp0"
+hint.ehci.0.addr=0xcd000000
+hint.ehci.0.irq=32
+hint.ehci.1.at="ixp0"
+hint.ehci.1.addr=0xce000000
+hint.ehci.1.irq=33
Modified: head/sys/arm/include/armreg.h
==============================================================================
--- head/sys/arm/include/armreg.h Sat Dec 20 03:02:32 2008 (r186351)
+++ head/sys/arm/include/armreg.h Sat Dec 20 03:26:09 2008 (r186352)
@@ -174,6 +174,7 @@
#define CPU_ID_IXP425_533 0x690541c0
#define CPU_ID_IXP425_400 0x690541d0
#define CPU_ID_IXP425_266 0x690541f0
+#define CPU_ID_IXP435 0x69054040
/* ARM3-specific coprocessor 15 registers */
#define ARM3_CP15_FLUSH 1
Modified: head/sys/arm/include/intr.h
==============================================================================
--- head/sys/arm/include/intr.h Sat Dec 20 03:02:32 2008 (r186351)
+++ head/sys/arm/include/intr.h Sat Dec 20 03:26:09 2008 (r186352)
@@ -39,6 +39,7 @@
#ifndef _MACHINE_INTR_H_
#define _MACHINE_INTR_H_
+/* XXX move to std.* files? */
#ifdef CPU_XSCALE_81342
#define NIRQ 128
#elif defined(CPU_XSCALE_PXA2X0)
@@ -46,7 +47,8 @@
#define NIRQ IRQ_GPIO_MAX
#elif defined(SOC_MV_DISCOVERY)
#define NIRQ 96
-#elif defined(CPU_ARM9) || defined(SOC_MV_KIRKWOOD)
+#elif defined(CPU_ARM9) || defined(SOC_MV_KIRKWOOD) || \
+ defined(CPU_XSCALE_IXP435)
#define NIRQ 64
#else
#define NIRQ 32
Modified: head/sys/arm/xscale/ixp425/avila_ata.c
==============================================================================
--- head/sys/arm/xscale/ixp425/avila_ata.c Sat Dec 20 03:02:32 2008 (r186351)
+++ head/sys/arm/xscale/ixp425/avila_ata.c Sat Dec 20 03:26:09 2008 (r186352)
@@ -67,13 +67,64 @@ __FBSDID("$FreeBSD$");
#include <dev/ata/ata-all.h>
#include <ata_if.h>
-#define AVILA_IDE_GPIN 12 /* GPIO pin # */
-#define AVILA_IDE_IRQ IXP425_INT_GPIO_12
-#define AVILA_IDE_CTRL 0x06 /* control register */
-
-#define PRONGHORN_IDE_GPIN 0 /* GPIO pin # */
-#define PRONGHORN_IDE_IRQ IXP425_INT_GPIO_0
-#define PRONGHORN_IDE_CNTRL 0x06 /* control register */
+#define AVILA_IDE_CTRL 0x06
+
+struct ata_config {
+ const char *desc; /* description for probe */
+ uint8_t gpin; /* GPIO pin */
+ uint8_t irq; /* IRQ */
+ uint32_t base16; /* CS base addr for 16-bit */
+ uint32_t size16; /* CS size for 16-bit */
+ uint32_t off16; /* CS offset for 16-bit */
+ uint32_t basealt; /* CS base addr for alt */
+ uint32_t sizealt; /* CS size for alt */
+ uint32_t offalt; /* CS offset for alt */
+};
+
+static const struct ata_config *
+ata_getconfig(struct ixp425_softc *sa)
+{
+ static const struct ata_config configs[] = {
+ { .desc = "Gateworks Avila IDE/CF Controller",
+ .gpin = 12,
+ .irq = IXP425_INT_GPIO_12,
+ .base16 = IXP425_EXP_BUS_CS1_HWBASE,
+ .size16 = IXP425_EXP_BUS_CS1_SIZE,
+ .off16 = EXP_TIMING_CS1_OFFSET,
+ .basealt = IXP425_EXP_BUS_CS2_HWBASE,
+ .sizealt = IXP425_EXP_BUS_CS2_SIZE,
+ .offalt = EXP_TIMING_CS2_OFFSET,
+ },
+ { .desc = "Gateworks Cambria IDE/CF Controller",
+ .gpin = 12,
+ .irq = IXP425_INT_GPIO_12,
+ .base16 = CAMBRIA_CFSEL0_HWBASE,
+ .size16 = CAMBRIA_CFSEL0_SIZE,
+ .off16 = EXP_TIMING_CS3_OFFSET,
+ .basealt = CAMBRIA_CFSEL1_HWBASE,
+ .sizealt = CAMBRIA_CFSEL1_SIZE,
+ .offalt = EXP_TIMING_CS4_OFFSET,
+ },
+ { .desc = "ADI Pronghorn Metro IDE/CF Controller",
+ .gpin = 0,
+ .irq = IXP425_INT_GPIO_0,
+ .base16 = IXP425_EXP_BUS_CS3_HWBASE,
+ .size16 = IXP425_EXP_BUS_CS3_SIZE,
+ .off16 = EXP_TIMING_CS3_OFFSET,
+ .basealt = IXP425_EXP_BUS_CS4_HWBASE,
+ .sizealt = IXP425_EXP_BUS_CS4_SIZE,
+ .offalt = EXP_TIMING_CS4_OFFSET,
+ },
+ };
+
+ /* XXX honor hint? (but then no multi-board support) */
+ /* XXX total hack */
+ if ((cpu_id() & CPU_ID_CPU_MASK) == CPU_ID_IXP435)
+ return &configs[1]; /* Cambria */
+ if (EXP_BUS_READ_4(sa, EXP_TIMING_CS2_OFFSET) != 0)
+ return &configs[0]; /* Avila */
+ return &configs[2]; /* Pronghorn */
+}
struct ata_avila_softc {
device_t sc_dev;
@@ -105,14 +156,14 @@ static int
ata_avila_probe(device_t dev)
{
struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
+ const struct ata_config *config;
- /* XXX any way to check? */
- if (EXP_BUS_READ_4(sa, EXP_TIMING_CS2_OFFSET) != 0)
- device_set_desc_copy(dev, "Gateworks Avila IDE/CF Controller");
- else
- device_set_desc_copy(dev,
- "ADI Pronghorn Metro IDE/CF Controller");
- return 0;
+ config = ata_getconfig(sa);
+ if (config != NULL) {
+ device_set_desc_copy(dev, config->desc);
+ return 0;
+ }
+ return ENXIO;
}
static int
@@ -120,41 +171,25 @@ ata_avila_attach(device_t dev)
{
struct ata_avila_softc *sc = device_get_softc(dev);
struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
- u_int32_t alt_t_off, ide_gpin, ide_irq;
+ const struct ata_config *config;
+
+ config = ata_getconfig(sa);
+ KASSERT(config != NULL, ("no board config"));
sc->sc_dev = dev;
/* NB: borrow from parent */
sc->sc_iot = sa->sc_iot;
sc->sc_exp_ioh = sa->sc_exp_ioh;
- if (EXP_BUS_READ_4(sc, EXP_TIMING_CS2_OFFSET) != 0) {
- /* Avila board */
- if (bus_space_map(sc->sc_iot, IXP425_EXP_BUS_CS1_HWBASE,
- IXP425_EXP_BUS_CS1_SIZE, 0, &sc->sc_ioh))
- panic("%s: unable to map Expansion Bus CS1 window",
- __func__);
- if (bus_space_map(sc->sc_iot, IXP425_EXP_BUS_CS2_HWBASE,
- IXP425_EXP_BUS_CS2_SIZE, 0, &sc->sc_alt_ioh))
- panic("%s: unable to map Expansion Bus CS2 window",
- __func__);
- ide_gpin = AVILA_IDE_GPIN;
- ide_irq = AVILA_IDE_IRQ;
- sc->sc_16bit_off = EXP_TIMING_CS1_OFFSET;
- alt_t_off = EXP_TIMING_CS2_OFFSET;
- } else {
- /* Pronghorn */
- if (bus_space_map(sc->sc_iot, IXP425_EXP_BUS_CS3_HWBASE,
- IXP425_EXP_BUS_CS3_SIZE, 0, &sc->sc_ioh))
- panic("%s: unable to map Expansion Bus CS3 window",
- __func__);
- if (bus_space_map(sc->sc_iot, IXP425_EXP_BUS_CS4_HWBASE,
- IXP425_EXP_BUS_CS4_SIZE, 0, &sc->sc_alt_ioh))
- panic("%s: unable to map Expansion Bus CS4 window",
- __func__);
- ide_gpin = PRONGHORN_IDE_GPIN;
- ide_irq = PRONGHORN_IDE_IRQ;
- sc->sc_16bit_off = EXP_TIMING_CS3_OFFSET;
- alt_t_off = EXP_TIMING_CS4_OFFSET;
- }
+
+ if (bus_space_map(sc->sc_iot, config->base16, config->size16,
+ 0, &sc->sc_ioh))
+ panic("%s: cannot map 16-bit window (0x%x/0x%x)",
+ __func__, config->base16, config->size16);
+ if (bus_space_map(sc->sc_iot, config->basealt, config->sizealt,
+ 0, &sc->sc_alt_ioh))
+ panic("%s: cannot map alt window (0x%x/0x%x)",
+ __func__, config->basealt, config->sizealt);
+ sc->sc_16bit_off = config->off16;
/*
* Craft special resource for ATA bus space ops
@@ -184,30 +219,30 @@ ata_avila_attach(device_t dev)
rman_set_bushandle(&sc->sc_alt_ata, sc->sc_alt_ioh);
GPIO_CONF_WRITE_4(sa, IXP425_GPIO_GPOER,
- GPIO_CONF_READ_4(sa, IXP425_GPIO_GPOER) | (1<<ide_gpin));
+ GPIO_CONF_READ_4(sa, IXP425_GPIO_GPOER) | (1<<config->gpin));
/* set interrupt type */
- GPIO_CONF_WRITE_4(sa, GPIO_TYPE_REG(ide_gpin),
- (GPIO_CONF_READ_4(sa, GPIO_TYPE_REG(ide_gpin)) &~
- GPIO_TYPE(ide_gpin, GPIO_TYPE_MASK)) |
- GPIO_TYPE(ide_gpin, GPIO_TYPE_EDG_RISING));
+ GPIO_CONF_WRITE_4(sa, GPIO_TYPE_REG(config->gpin),
+ (GPIO_CONF_READ_4(sa, GPIO_TYPE_REG(config->gpin)) &~
+ GPIO_TYPE(config->gpin, GPIO_TYPE_MASK)) |
+ GPIO_TYPE(config->gpin, GPIO_TYPE_EDG_RISING));
/* clear ISR */
- GPIO_CONF_WRITE_4(sa, IXP425_GPIO_GPISR, (1<<ide_gpin));
+ GPIO_CONF_WRITE_4(sa, IXP425_GPIO_GPISR, (1<<config->gpin));
/* configure CS1/3 window, leaving timing unchanged */
EXP_BUS_WRITE_4(sc, sc->sc_16bit_off,
EXP_BUS_READ_4(sc, sc->sc_16bit_off) |
EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN);
/* configure CS2/4 window, leaving timing unchanged */
- EXP_BUS_WRITE_4(sc, alt_t_off,
- EXP_BUS_READ_4(sc, alt_t_off) |
+ EXP_BUS_WRITE_4(sc, config->offalt,
+ EXP_BUS_READ_4(sc, config->offalt) |
EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN);
/* setup interrupt */
sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->sc_rid,
- ide_irq, ide_irq, 1, RF_ACTIVE);
+ config->irq, config->irq, 1, RF_ACTIVE);
if (!sc->sc_irq)
- panic("Unable to allocate irq %u.\n", ide_irq);
+ panic("Unable to allocate irq %u.\n", config->irq);
bus_setup_intr(dev, sc->sc_irq,
INTR_TYPE_BIO | INTR_MPSAFE | INTR_ENTROPY,
NULL, ata_avila_intr, sc, &sc->sc_ih);
@@ -230,9 +265,9 @@ ata_avila_detach(device_t dev)
/* detach & delete all children */
if (device_get_children(dev, &children, &nc) == 0) {
- if (nc > 0)
- device_delete_child(dev, children[0]);
- free(children, M_TEMP);
+ if (nc > 0)
+ device_delete_child(dev, children[0]);
+ free(children, M_TEMP);
}
bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
@@ -308,7 +343,7 @@ ata_avila_teardown_intr(device_t dev, de
/*
* Enable/disable 16-bit ops on the expansion bus.
*/
-static void __inline
+static __inline void
enable_16(struct ata_avila_softc *sc)
{
EXP_BUS_WRITE_4(sc, sc->sc_16bit_off,
@@ -316,7 +351,7 @@ enable_16(struct ata_avila_softc *sc)
DELAY(100); /* XXX? */
}
-static void __inline
+static __inline void
disable_16(struct ata_avila_softc *sc)
{
DELAY(100); /* XXX? */
Modified: head/sys/arm/xscale/ixp425/avila_led.c
==============================================================================
--- head/sys/arm/xscale/ixp425/avila_led.c Sat Dec 20 03:02:32 2008 (r186351)
+++ head/sys/arm/xscale/ixp425/avila_led.c Sat Dec 20 03:26:09 2008 (r186352)
@@ -37,22 +37,19 @@ __FBSDID("$FreeBSD$");
#include <dev/led/led.h>
#define GPIO_LED_STATUS 3
-#define GPIO_LED_STATUS_BIT (1U << GPIO_LED_STATUS)
-
-static struct cdev *gpioled;
+#define GPIO_LED_STATUS_BIT (1U << GPIO_LED_STATUS)
struct led_avila_softc {
device_t sc_dev;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_gpio_ioh;
+ struct cdev *sc_led;
};
-static struct led_avila_softc *led_avila_sc = NULL;
-
static void
-led_func(void *unused, int onoff)
+led_func(void *arg, int onoff)
{
- struct led_avila_softc *sc = led_avila_sc;
+ struct led_avila_softc *sc = arg;
uint32_t reg;
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
@@ -66,7 +63,7 @@ led_func(void *unused, int onoff)
static int
led_avila_probe(device_t dev)
{
- device_set_desc(dev, "Gateworks Avila GPIO connected LED");
+ device_set_desc(dev, "Gateworks Avila Front Panel LED");
return (0);
}
@@ -75,31 +72,35 @@ led_avila_attach(device_t dev)
{
struct led_avila_softc *sc = device_get_softc(dev);
struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
- void *led = NULL;
- uint32_t reg;
-
- led_avila_sc = sc;
sc->sc_dev = dev;
sc->sc_iot = sa->sc_iot;
sc->sc_gpio_ioh = sa->sc_gpio_ioh;
/* Configure LED GPIO pin as output */
- reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER);
- reg &= ~GPIO_LED_STATUS_BIT;
- GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER, reg);
+ GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER,
+ GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER) &~ GPIO_LED_STATUS_BIT);
- gpioled = led_create(led_func, led, "gpioled");
+ sc->sc_led = led_create(led_func, sc, "gpioled");
- /* Turn on LED */
- led_func(led, 1);
+ led_func(sc, 1); /* Turn on LED */
return (0);
}
+static void
+led_avila_detach(device_t dev)
+{
+ struct led_avila_softc *sc = device_get_softc(dev);
+
+ if (sc->sc_led != NULL)
+ led_destroy(sc->sc_led);
+}
+
static device_method_t led_avila_methods[] = {
DEVMETHOD(device_probe, led_avila_probe),
DEVMETHOD(device_attach, led_avila_attach),
+ DEVMETHOD(device_detach, led_avila_detach),
{0, 0},
};
Modified: head/sys/arm/xscale/ixp425/avila_machdep.c
==============================================================================
--- head/sys/arm/xscale/ixp425/avila_machdep.c Sat Dec 20 03:02:32 2008 (r186351)
+++ head/sys/arm/xscale/ixp425/avila_machdep.c Sat Dec 20 03:26:09 2008 (r186352)
@@ -95,6 +95,11 @@ __FBSDID("$FreeBSD$");
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
+/* kernel text starts where we were loaded at boot */
+#define KERNEL_TEXT_OFF (KERNPHYSADDR - PHYSADDR)
+#define KERNEL_TEXT_BASE (KERNBASE + KERNEL_TEXT_OFF)
+#define KERNEL_TEXT_PHYS (PHYSADDR + KERNEL_TEXT_OFF)
+
#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */
#define KERNEL_PT_IO 1
#define KERNEL_PT_IO_NUM 3
@@ -142,114 +147,109 @@ static struct trapframe proc0_tf;
/* Static device mappings. */
static const struct pmap_devmap ixp425_devmap[] = {
/* Physical/Virtual address for I/O space */
- {
- IXP425_IO_VBASE,
- IXP425_IO_HWBASE,
- IXP425_IO_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
+ { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
/* Expansion Bus */
- {
- IXP425_EXP_VBASE,
- IXP425_EXP_HWBASE,
- IXP425_EXP_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
+ { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
/* IXP425 PCI Configuration */
- {
- IXP425_PCI_VBASE,
- IXP425_PCI_HWBASE,
- IXP425_PCI_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
+ { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
/* SDRAM Controller */
- {
- IXP425_MCU_VBASE,
- IXP425_MCU_HWBASE,
- IXP425_MCU_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
+ { IXP425_MCU_VBASE, IXP425_MCU_HWBASE, IXP425_MCU_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
/* PCI Memory Space */
- {
- IXP425_PCI_MEM_VBASE,
- IXP425_PCI_MEM_HWBASE,
- IXP425_PCI_MEM_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
+ { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
+ /* Q-Mgr Memory Space */
+ { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
/* NPE-A Memory Space */
- {
- IXP425_NPE_A_VBASE,
- IXP425_NPE_A_HWBASE,
- IXP425_NPE_A_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
+ { IXP425_NPE_A_VBASE, IXP425_NPE_A_HWBASE, IXP425_NPE_A_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
/* NPE-B Memory Space */
- {
- IXP425_NPE_B_VBASE,
- IXP425_NPE_B_HWBASE,
- IXP425_NPE_B_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
+ { IXP425_NPE_B_VBASE, IXP425_NPE_B_HWBASE, IXP425_NPE_B_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
/* NPE-C Memory Space */
- {
- IXP425_NPE_C_VBASE,
- IXP425_NPE_C_HWBASE,
- IXP425_NPE_C_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
- /* MAC-A Memory Space */
- {
- IXP425_MAC_A_VBASE,
- IXP425_MAC_A_HWBASE,
- IXP425_MAC_A_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
+ { IXP425_NPE_C_VBASE, IXP425_NPE_C_HWBASE, IXP425_NPE_C_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
/* MAC-B Memory Space */
- {
- IXP425_MAC_B_VBASE,
- IXP425_MAC_B_HWBASE,
- IXP425_MAC_B_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
- /* Q-Mgr Memory Space */
- {
- IXP425_QMGR_VBASE,
- IXP425_QMGR_HWBASE,
- IXP425_QMGR_SIZE,
- VM_PROT_READ|VM_PROT_WRITE,
- PTE_NOCACHE,
- },
-
- {
- 0,
- 0,
- 0,
- 0,
- 0,
- }
+ { IXP425_MAC_B_VBASE, IXP425_MAC_B_HWBASE, IXP425_MAC_B_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+ /* MAC-C Memory Space */
+ { IXP425_MAC_C_VBASE, IXP425_MAC_C_HWBASE, IXP425_MAC_C_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
+ { 0 },
};
-#define SDRAM_START 0x10000000
+/* Static device mappings. */
+static const struct pmap_devmap ixp435_devmap[] = {
+ /* Physical/Virtual address for I/O space */
+ { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
+ /* Expansion Bus */
+ { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
+ /* IXP425 PCI Configuration */
+ { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
+ /* DDRII Controller NB: mapped same place as IXP425 */
+ { IXP425_MCU_VBASE, IXP435_MCU_HWBASE, IXP425_MCU_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
+ /* PCI Memory Space */
+ { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
+ /* Q-Mgr Memory Space */
+ { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
+ /* NPE-A Memory Space */
+ { IXP425_NPE_A_VBASE, IXP425_NPE_A_HWBASE, IXP425_NPE_A_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+ /* NPE-C Memory Space */
+ { IXP425_NPE_C_VBASE, IXP425_NPE_C_HWBASE, IXP425_NPE_C_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
+ /* MAC-C Memory Space */
+ { IXP425_MAC_C_VBASE, IXP425_MAC_C_HWBASE, IXP425_MAC_C_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+ /* MAC-B Memory Space */
+ { IXP425_MAC_B_VBASE, IXP425_MAC_B_HWBASE, IXP425_MAC_B_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+ /* MAC-A Memory Space */
+ { IXP435_MAC_A_VBASE, IXP435_MAC_A_HWBASE, IXP435_MAC_A_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
+ /* USB1 Memory Space */
+ { IXP435_USB1_VBASE, IXP435_USB1_HWBASE, IXP435_USB1_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+ /* USB2 Memory Space */
+ { IXP435_USB2_VBASE, IXP435_USB2_HWBASE, IXP435_USB2_SIZE,
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+
+ { 0 }
+};
extern vm_offset_t xscale_cache_clean_addr;
void *
initarm(void *arg, void *arg2)
{
+#define next_chunk2(a,b) (((a) + (b)) &~ ((b)-1))
+#define next_page(a) next_chunk2(a,PAGE_SIZE)
struct pv_addr kernel_l1pt;
int loop, i;
u_int l1pagetable;
@@ -260,25 +260,40 @@ initarm(void *arg, void *arg2)
vm_offset_t lastaddr;
uint32_t memsize;
- set_cpufuncs();
+ set_cpufuncs(); /* NB: sets cputype */
lastaddr = fake_preload_metadata();
pcpu_init(pcpup, 0, sizeof(struct pcpu));
PCPU_SET(curthread, &thread0);
- freemempos = 0x10200000;
- /* Define a macro to simplify memory allocation */
-#define valloc_pages(var, np) \
- alloc_pages((var).pv_pa, (np)); \
- (var).pv_va = (var).pv_pa + 0xb0000000;
-
-#define alloc_pages(var, np) \
- freemempos -= (np * PAGE_SIZE); \
- (var) = freemempos; \
- memset((char *)(var), 0, ((np) * PAGE_SIZE));
+ /*
+ * We allocate memory downwards from where we were loaded
+ * by RedBoot; first the L1 page table, then NUM_KERNEL_PTS
+ * entries in the L2 page table. Past that we re-align the
+ * allocation boundary so later data structures (stacks, etc)
+ * can be mapped with different attributes (write-back vs
+ * write-through). Note this leaves a gap for expansion
+ * (or might be repurposed).
+ */
+ freemempos = KERNPHYSADDR;
+
+ /* macros to simplify initial memory allocation */
+#define alloc_pages(var, np) do { \
+ freemempos -= (np * PAGE_SIZE); \
+ (var) = freemempos; \
+ /* NB: this works because locore maps PA=VA */ \
+ memset((char *)(var), 0, ((np) * PAGE_SIZE)); \
+} while (0)
+#define valloc_pages(var, np) do { \
+ alloc_pages((var).pv_pa, (np)); \
+ (var).pv_va = (var).pv_pa + (KERNVIRTADDR - KERNPHYSADDR); \
+} while (0)
+ /* force L1 page table alignment */
while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
freemempos -= PAGE_SIZE;
+ /* allocate contiguous L1 page table */
valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
+ /* now allocate L2 page tables; they are linked to L1 below */
for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
valloc_pages(kernel_pt_table[loop],
@@ -288,11 +303,18 @@ initarm(void *arg, void *arg2)
(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
L2_TABLE_SIZE_REAL;
kernel_pt_table[loop].pv_va =
- kernel_pt_table[loop].pv_pa + 0xb0000000;
+ kernel_pt_table[loop].pv_pa +
+ (KERNVIRTADDR - KERNPHYSADDR);
}
}
- freemem_pt = freemempos;
- freemempos = 0x10100000;
+ freemem_pt = freemempos; /* base of allocated pt's */
+
+ /*
+ * Re-align allocation boundary so we can map the area
+ * write-back instead of write-through for the stacks and
+ * related structures allocated below.
+ */
+ freemempos = PHYSADDR + 0x100000;
/*
* Allocate a page for the system page mapped to V0x00000000
* This page will just contain the system vectors and can be
@@ -308,30 +330,25 @@ initarm(void *arg, void *arg2)
alloc_pages(minidataclean.pv_pa, 1);
valloc_pages(msgbufpv, round_page(MSGBUF_SIZE) / PAGE_SIZE);
#ifdef ARM_USE_SMALL_ALLOC
+#error "I am broken" /* XXX save people grief */
freemempos -= PAGE_SIZE;
freemem_pt = trunc_page(freemem_pt);
freemem_after = freemempos - ((freemem_pt - 0x10100000) /
PAGE_SIZE) * sizeof(struct arm_small_page);
- arm_add_smallalloc_pages((void *)(freemem_after + 0xb0000000)
+ arm_add_smallalloc_pages((void *)(freemem_after + (KERNVIRTADDR - KERNPHYSADDR)
, (void *)0xc0100000, freemem_pt - 0x10100000, 1);
freemem_after -= ((freemem_after - 0x10001000) / PAGE_SIZE) *
sizeof(struct arm_small_page);
- arm_add_smallalloc_pages((void *)(freemem_after + 0xb0000000)
+ arm_add_smallalloc_pages((void *)(freemem_after + (KEYVIRTADDR - KERNPHYSADDR))
, (void *)0xc0001000, trunc_page(freemem_after) - 0x10001000, 0);
freemempos = trunc_page(freemem_after);
freemempos -= PAGE_SIZE;
#endif
- /*
- * Allocate memory for the l1 and l2 page tables. The scheme to avoid
- * wasting memory by allocating the l1pt on the first 16k memory was
- * taken from NetBSD rpc_machdep.c. NKPT should be greater than 12 for
- * this to work (which is supposed to be the case).
- */
/*
- * Now we start construction of the L1 page table
- * We start by mapping the L2 page tables into the L1.
- * This means that we can replace L1 mappings later on if necessary
+ * Now construct the L1 page table. First map the L2
+ * page tables into the L1 so we can replace L1 mappings
+ * later on if necessary
*/
l1pagetable = kernel_l1pt.pv_va;
@@ -339,30 +356,28 @@ initarm(void *arg, void *arg2)
pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1),
&kernel_pt_table[KERNEL_PT_SYS]);
pmap_link_l2pt(l1pagetable, IXP425_IO_VBASE,
- &kernel_pt_table[KERNEL_PT_IO]);
+ &kernel_pt_table[KERNEL_PT_IO]);
pmap_link_l2pt(l1pagetable, IXP425_MCU_VBASE,
- &kernel_pt_table[KERNEL_PT_IO + 1]);
+ &kernel_pt_table[KERNEL_PT_IO + 1]);
pmap_link_l2pt(l1pagetable, IXP425_PCI_MEM_VBASE,
- &kernel_pt_table[KERNEL_PT_IO + 2]);
+ &kernel_pt_table[KERNEL_PT_IO + 2]);
pmap_link_l2pt(l1pagetable, KERNBASE,
&kernel_pt_table[KERNEL_PT_BEFOREKERN]);
- pmap_map_chunk(l1pagetable, KERNBASE, SDRAM_START, 0x100000,
+ pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR, 0x100000,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
- pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, SDRAM_START + 0x100000,
+ pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, PHYSADDR + 0x100000,
0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
- pmap_map_chunk(l1pagetable, KERNBASE + 0x200000, SDRAM_START + 0x200000,
- (((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE) & ~(L1_S_SIZE - 1),
+ pmap_map_chunk(l1pagetable, KERNEL_TEXT_BASE, KERNEL_TEXT_PHYS,
+ next_chunk2(((uint32_t)lastaddr) - KERNEL_TEXT_BASE, L1_S_SIZE),
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
- freemem_after = ((int)lastaddr + PAGE_SIZE) & ~(PAGE_SIZE - 1);
- afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & ~(L1_S_SIZE
- - 1));
+ freemem_after = next_page((int)lastaddr);
+ afterkern = round_page(next_chunk2((vm_offset_t)lastaddr, L1_S_SIZE));
for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
&kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
}
pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
-
#ifdef ARM_USE_SMALL_ALLOC
if ((freemem_after + 2 * PAGE_SIZE) <= afterkern) {
@@ -380,7 +395,10 @@ initarm(void *arg, void *arg2)
/* Map the vector page. */
pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
- pmap_devmap_bootstrap(l1pagetable, ixp425_devmap);
+ if (cpu_is_ixp43x())
+ pmap_devmap_bootstrap(l1pagetable, ixp435_devmap);
+ else
+ pmap_devmap_bootstrap(l1pagetable, ixp425_devmap);
/*
* Give the XScale global cache clean code an appropriately
* sized chunk of unmapped VA space starting at 0xff000000
@@ -392,6 +410,7 @@ initarm(void *arg, void *arg2)
setttb(kernel_l1pt.pv_pa);
cpu_tlb_flushID();
cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
+
/*
* Pages were allocated during the secondary bootstrap for the
* stacks for different CPU modes.
@@ -400,16 +419,9 @@ initarm(void *arg, void *arg2)
* Since the ARM stacks use STMFD etc. we must set r13 to the top end
* of the stack memory.
*/
-
-
- set_stackptr(PSR_IRQ32_MODE,
- irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
- set_stackptr(PSR_ABT32_MODE,
- abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE);
- set_stackptr(PSR_UND32_MODE,
- undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE);
-
-
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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