svn commit: r366794 - head/sys/riscv/riscv

[Mitchell Horne]

Author: mhorne
Date: Sat Oct 17 17:31:06 2020
New Revision: 366794
URL: https://svnweb.freebsd.org/changeset/base/366794

Log:
  riscv: zero reserved PTE bits for L2 PTEs
  
  As was done for L3 PTEs in r362853, mask out the reserved bits when
  extracting the physical address from an L2 PTE. Future versions of the
  spec or custom implementations may make use of these reserved bits, in
  which case the resulting physical address could be incorrect.
  
  Submitted by:	Nathaniel Filardo <nwf20 at cl.cam.ac.uk>
  Reviewed by:	kp, mhorne
  Differential Revision:	https://reviews.freebsd.org/D26607

Modified:
  head/sys/riscv/riscv/pmap.c

Modified: head/sys/riscv/riscv/pmap.c
==============================================================================
--- head/sys/riscv/riscv/pmap.c	Sat Oct 17 13:06:29 2020	(r366793)
+++ head/sys/riscv/riscv/pmap.c	Sat Oct 17 17:31:06 2020	(r366794)
@@ -342,6 +342,8 @@ pagezero(void *p)
 
 #define	PTE_TO_PHYS(pte) \
     ((((pte) & ~PTE_HI_MASK) >> PTE_PPN0_S) * PAGE_SIZE)
+#define	L2PTE_TO_PHYS(l2) \
+    ((((l2) & ~PTE_HI_MASK) >> PTE_PPN1_S) << L2_SHIFT)
 
 static __inline pd_entry_t *
 pmap_l1(pmap_t pmap, vm_offset_t va)
@@ -477,7 +479,7 @@ pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
 		("Invalid bootstrap L2 table"));
 
 	/* L2 is superpages */
-	ret = (l2[l2_slot] >> PTE_PPN1_S) << L2_SHIFT;
+	ret = L2PTE_TO_PHYS(l2[l2_slot]);
 	ret += (va & L2_OFFSET);
 
 	return (ret);
@@ -825,7 +827,7 @@ pmap_extract(pmap_t pmap, vm_offset_t va)
 			}
 		} else {
 			/* L2 is superpages */
-			pa = (l2 >> PTE_PPN1_S) << L2_SHIFT;
+			pa = L2PTE_TO_PHYS(l2);
 			pa |= (va & L2_OFFSET);
 		}
 	}
@@ -877,7 +879,7 @@ pmap_kextract(vm_offset_t va)
 			panic("pmap_kextract: No l2");
 		if ((pmap_load(l2) & PTE_RX) != 0) {
 			/* superpages */
-			pa = (pmap_load(l2) >> PTE_PPN1_S) << L2_SHIFT;
+			pa = L2PTE_TO_PHYS(pmap_load(l2));
 			pa |= (va & L2_OFFSET);
 			return (pa);
 		}