svn commit: r362129 - in head/sys/x86: include x86

[Konstantin Belousov]

Author: kib
Date: Fri Jun 12 22:12:57 2020
New Revision: 362129
URL: https://svnweb.freebsd.org/changeset/base/362129

Log:
  x86: add bits definitions for SRBDS mitigation control.
  
  See https://software.intel.com/security-software-guidance/insights/deep-dive-special-register-buffer-data-sampling
  
  Reviewed by:	markj
  Sponsored by:	The FreeBSD Foundation
  MFC after:	1 week
  Differential revision:	https://reviews.freebsd.org/D25221

Modified:
  head/sys/x86/include/specialreg.h
  head/sys/x86/x86/identcpu.c

Modified: head/sys/x86/include/specialreg.h
==============================================================================
--- head/sys/x86/include/specialreg.h	Fri Jun 12 22:10:03 2020	(r362128)
+++ head/sys/x86/include/specialreg.h	Fri Jun 12 22:12:57 2020	(r362129)
@@ -477,6 +477,7 @@
 #define	CPUID_STDEXT3_AVX5124FMAPS	0x00000008
 #define	CPUID_STDEXT3_FSRM		0x00000010
 #define	CPUID_STDEXT3_AVX512VP2INTERSECT	0x00000100
+#define	CPUID_STDEXT3_MCUOPT		0x00000200
 #define	CPUID_STDEXT3_MD_CLEAR		0x00000400
 #define	CPUID_STDEXT3_TSXFA		0x00002000
 #define	CPUID_STDEXT3_PCONFIG		0x00040000
@@ -555,6 +556,7 @@
 #define	MSR_BBL_CR_BUSY		0x11b
 #define	MSR_BBL_CR_CTL3		0x11e
 #define	MSR_IA32_TSX_CTRL	0x122
+#define	MSR_IA32_MCU_OPT_CTRL	0x123
 #define	MSR_SYSENTER_CS_MSR	0x174
 #define	MSR_SYSENTER_ESP_MSR	0x175
 #define	MSR_SYSENTER_EIP_MSR	0x176
@@ -796,6 +798,9 @@
 
 /* MSR IA32_FLUSH_CMD */
 #define	IA32_FLUSH_CMD_L1D	0x00000001
+
+/* MSR IA32_MCU_OPT_CTRL */
+#define	IA32_RNGDS_MITG_DIS	0x00000001
 
 /* MSR IA32_HWP_CAPABILITIES */
 #define	IA32_HWP_CAPABILITIES_HIGHEST_PERFORMANCE(x)	(((x) >> 0) & 0xff)

Modified: head/sys/x86/x86/identcpu.c
==============================================================================
--- head/sys/x86/x86/identcpu.c	Fri Jun 12 22:10:03 2020	(r362128)
+++ head/sys/x86/x86/identcpu.c	Fri Jun 12 22:12:57 2020	(r362129)
@@ -1028,6 +1028,7 @@ printcpuinfo(void)
 				       "\004AVX512_4FMAPS"
 				       "\005FSRM"
 				       "\011AVX512VP2INTERSECT"
+				       "\012MCUOPT"
 				       "\013MD_CLEAR"
 				       "\016TSXFA"
 				       "\023PCONFIG"