svn commit: r356940 - in head: stand/i386/libi386 sys/amd64/amd64 sys/i386/i386 sys/x86/cpufreq sys/x86/include sys/x86/x86
Konstantin Belousov
kib at FreeBSD.org
Tue Jan 21 13:22:39 UTC 2020
Author: kib
Date: Tue Jan 21 13:22:35 2020
New Revision: 356940
URL: https://svnweb.freebsd.org/changeset/base/356940
Log:
Add support for Hygon Dhyana Family 18h processor.
As a new x86 CPU vendor, Chengdu Haiguang IC Design Co., Ltd (Hygon)
is a joint venture between AMD and Haiguang Information Technology Co.,
Ltd., aims at providing x86 processors for China server market.
The first generation Hygon processor(Dhyana) shares most architecture
with AMD's family 17h, but with different CPU vendor ID("HygonGenuine")
and PCI vendor ID(0x1d94) and family series number 18h(Hygon negotiated
with AMD to confirm that only Hygon use family 18h).
To enable Hygon Dhyana support in FreeBSD, add new definitions
HYGON_VENDOR_ID("HygonGenuine") and X86_VENDOR_HYGON(0x1d94) to identify
Hygon Dhyana CPU.
Initialize the CPU features(topology, local APIC ext, MSI, TSC, hwpstate,
MCA, DEBUG_CTL, etc) for amd64 and i386 mode by sharing the code path of
AMD family 17h.
The changes have been applied on FreeBSD 13.0-CURRENT and tested
successfully on Hygon Dhyana processor.
References:
[1] Linux kernel patches for Hygon Dhyana, merged in 4.20:
https://git.kernel.org/tip/c9661c1e80b609cd038db7c908e061f0535804ef
[2] MSR and CPUID definition:
https://www.amd.com/system/files/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf
Submitted by: Pu Wen <puwen at hygon.cn>
MFC after: 1 week
Differential revision: https://reviews.freebsd.org/D23163
Modified:
head/stand/i386/libi386/bootinfo64.c
head/sys/amd64/amd64/initcpu.c
head/sys/i386/i386/machdep.c
head/sys/x86/cpufreq/hwpstate.c
head/sys/x86/include/cputypes.h
head/sys/x86/include/specialreg.h
head/sys/x86/x86/identcpu.c
head/sys/x86/x86/local_apic.c
head/sys/x86/x86/mca.c
head/sys/x86/x86/mp_x86.c
head/sys/x86/x86/msi.c
head/sys/x86/x86/tsc.c
Modified: head/stand/i386/libi386/bootinfo64.c
==============================================================================
--- head/stand/i386/libi386/bootinfo64.c Tue Jan 21 12:00:34 2020 (r356939)
+++ head/stand/i386/libi386/bootinfo64.c Tue Jan 21 13:22:35 2020 (r356940)
@@ -158,6 +158,7 @@ bi_checkcpu(void)
/* Check for vendors that support AMD features. */
if (strncmp(cpu_vendor, INTEL_VENDOR_ID, 12) != 0 &&
strncmp(cpu_vendor, AMD_VENDOR_ID, 12) != 0 &&
+ strncmp(cpu_vendor, HYGON_VENDOR_ID, 12) != 0 &&
strncmp(cpu_vendor, CENTAUR_VENDOR_ID, 12) != 0)
return (0);
Modified: head/sys/amd64/amd64/initcpu.c
==============================================================================
--- head/sys/amd64/amd64/initcpu.c Tue Jan 21 12:00:34 2020 (r356939)
+++ head/sys/amd64/amd64/initcpu.c Tue Jan 21 13:22:35 2020 (r356940)
@@ -171,7 +171,8 @@ init_amd(void)
*/
if (lower_sharedpage_init == 0) {
lower_sharedpage_init = 1;
- if (CPUID_TO_FAMILY(cpu_id) == 0x17) {
+ if (CPUID_TO_FAMILY(cpu_id) == 0x17 ||
+ CPUID_TO_FAMILY(cpu_id) == 0x18) {
hw_lower_amd64_sharedpage = 1;
}
}
@@ -259,6 +260,7 @@ initializecpu(void)
amd64_syscall_ret_flush_l1d_recalc();
switch (cpu_vendor_id) {
case CPU_VENDOR_AMD:
+ case CPU_VENDOR_HYGON:
init_amd();
break;
case CPU_VENDOR_CENTAUR:
Modified: head/sys/i386/i386/machdep.c
==============================================================================
--- head/sys/i386/i386/machdep.c Tue Jan 21 12:00:34 2020 (r356939)
+++ head/sys/i386/i386/machdep.c Tue Jan 21 13:22:35 2020 (r356940)
@@ -1607,8 +1607,9 @@ DB_SHOW_COMMAND(sysregs, db_show_sysregs)
if (cpu_feature2 & (CPUID2_VMX | CPUID2_SMX))
db_printf("FEATURES_CTL\t0x%016llx\n",
rdmsr(MSR_IA32_FEATURE_CONTROL));
- if ((cpu_vendor_id == CPU_VENDOR_INTEL ||
- cpu_vendor_id == CPU_VENDOR_AMD) && CPUID_TO_FAMILY(cpu_id) >= 6)
+ if (((cpu_vendor_id == CPU_VENDOR_INTEL ||
+ cpu_vendor_id == CPU_VENDOR_AMD) && CPUID_TO_FAMILY(cpu_id) >= 6) ||
+ cpu_vendor_id == CPU_VENDOR_HYGON)
db_printf("DEBUG_CTL\t0x%016llx\n", rdmsr(MSR_DEBUGCTLMSR));
if (cpu_feature & CPUID_PAT)
db_printf("PAT\t0x%016llx\n", rdmsr(MSR_PAT));
Modified: head/sys/x86/cpufreq/hwpstate.c
==============================================================================
--- head/sys/x86/cpufreq/hwpstate.c Tue Jan 21 12:00:34 2020 (r356939)
+++ head/sys/x86/cpufreq/hwpstate.c Tue Jan 21 13:22:35 2020 (r356940)
@@ -315,7 +315,8 @@ hwpstate_identify(driver_t *driver, device_t parent)
if (device_find_child(parent, "hwpstate", -1) != NULL)
return;
- if (cpu_vendor_id != CPU_VENDOR_AMD || CPUID_TO_FAMILY(cpu_id) < 0x10)
+ if ((cpu_vendor_id != CPU_VENDOR_AMD || CPUID_TO_FAMILY(cpu_id) < 0x10) &&
+ cpu_vendor_id != CPU_VENDOR_HYGON)
return;
/*
@@ -446,6 +447,7 @@ hwpstate_get_info_from_msr(device_t dev)
hwpstate_set[i].freq = (100 * (fid + 0x10)) >> did;
break;
case 0x17:
+ case 0x18:
did = AMD_17H_CUR_DID(msr);
if (did == 0) {
HWPSTATE_DEBUG(dev, "unexpected did: 0\n");
@@ -455,8 +457,10 @@ hwpstate_get_info_from_msr(device_t dev)
hwpstate_set[i].freq = (200 * fid) / did;
break;
default:
- HWPSTATE_DEBUG(dev, "get_info_from_msr: AMD family"
- " 0x%02x CPUs are not supported yet\n", family);
+ HWPSTATE_DEBUG(dev, "get_info_from_msr: %s family"
+ " 0x%02x CPUs are not supported yet\n",
+ cpu_vendor_id == CPU_VENDOR_HYGON ? "Hygon" : "AMD",
+ family);
return (ENXIO);
}
hwpstate_set[i].pstate_id = i;
Modified: head/sys/x86/include/cputypes.h
==============================================================================
--- head/sys/x86/include/cputypes.h Tue Jan 21 12:00:34 2020 (r356939)
+++ head/sys/x86/include/cputypes.h Tue Jan 21 13:22:35 2020 (r356940)
@@ -45,5 +45,6 @@
#define CPU_VENDOR_INTEL 0x8086 /* Intel */
#define CPU_VENDOR_RISE 0xdead2bad /* Rise */
#define CPU_VENDOR_CENTAUR CPU_VENDOR_IDT
+#define CPU_VENDOR_HYGON 0x1d94 /* Hygon */
#endif /* !_X86_CPUTYPES_H_ */
Modified: head/sys/x86/include/specialreg.h
==============================================================================
--- head/sys/x86/include/specialreg.h Tue Jan 21 12:00:34 2020 (r356939)
+++ head/sys/x86/include/specialreg.h Tue Jan 21 13:22:35 2020 (r356940)
@@ -511,6 +511,7 @@
#define SIS_VENDOR_ID "SiS SiS SiS "
#define TRANSMETA_VENDOR_ID "GenuineTMx86"
#define UMC_VENDOR_ID "UMC UMC UMC "
+#define HYGON_VENDOR_ID "HygonGenuine"
/*
* Model-specific registers for the i386 family
Modified: head/sys/x86/x86/identcpu.c
==============================================================================
--- head/sys/x86/x86/identcpu.c Tue Jan 21 12:00:34 2020 (r356939)
+++ head/sys/x86/x86/identcpu.c Tue Jan 21 13:22:35 2020 (r356940)
@@ -223,6 +223,7 @@ static struct {
} cpu_vendors[] = {
{ INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
{ AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
+ { HYGON_VENDOR_ID, CPU_VENDOR_HYGON }, /* HygonGenuine*/
{ CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
#ifdef __i386__
{ NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
@@ -682,6 +683,18 @@ printcpuinfo(void)
}
break;
#endif
+ case CPU_VENDOR_HYGON:
+ strcpy(cpu_model, "Hygon ");
+#ifdef __i386__
+ strcat(cpu_model, "Unknown");
+#else
+ if ((cpu_id & 0xf00) == 0xf00)
+ strcat(cpu_model, "AMD64 Processor");
+ else
+ strcat(cpu_model, "Unknown");
+#endif
+ break;
+
default:
strcat(cpu_model, "Unknown");
break;
@@ -741,6 +754,7 @@ printcpuinfo(void)
if (cpu_vendor_id == CPU_VENDOR_INTEL ||
cpu_vendor_id == CPU_VENDOR_AMD ||
+ cpu_vendor_id == CPU_VENDOR_HYGON ||
cpu_vendor_id == CPU_VENDOR_CENTAUR ||
#ifdef __i386__
cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
@@ -1095,7 +1109,8 @@ printcpuinfo(void)
print_svm_info();
if ((cpu_feature & CPUID_HTT) &&
- cpu_vendor_id == CPU_VENDOR_AMD)
+ (cpu_vendor_id == CPU_VENDOR_AMD ||
+ cpu_vendor_id == CPU_VENDOR_HYGON))
cpu_feature &= ~CPUID_HTT;
/*
@@ -1125,7 +1140,8 @@ printcpuinfo(void)
printf("\n");
if (bootverbose) {
- if (cpu_vendor_id == CPU_VENDOR_AMD)
+ if (cpu_vendor_id == CPU_VENDOR_AMD ||
+ cpu_vendor_id == CPU_VENDOR_HYGON)
print_AMD_info();
else if (cpu_vendor_id == CPU_VENDOR_INTEL)
print_INTEL_info();
@@ -1631,6 +1647,7 @@ finishidentcpu(void)
if (cpu_high > 0 &&
(cpu_vendor_id == CPU_VENDOR_INTEL ||
cpu_vendor_id == CPU_VENDOR_AMD ||
+ cpu_vendor_id == CPU_VENDOR_HYGON ||
cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
cpu_vendor_id == CPU_VENDOR_CENTAUR ||
cpu_vendor_id == CPU_VENDOR_NSC)) {
@@ -1641,6 +1658,7 @@ finishidentcpu(void)
#else
if (cpu_vendor_id == CPU_VENDOR_INTEL ||
cpu_vendor_id == CPU_VENDOR_AMD ||
+ cpu_vendor_id == CPU_VENDOR_HYGON ||
cpu_vendor_id == CPU_VENDOR_CENTAUR) {
do_cpuid(0x80000000, regs);
cpu_exthigh = regs[0];
@@ -1760,7 +1778,8 @@ int
pti_get_default(void)
{
- if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0)
+ if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 ||
+ strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0)
return (0);
if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
return (0);
Modified: head/sys/x86/x86/local_apic.c
==============================================================================
--- head/sys/x86/x86/local_apic.c Tue Jan 21 12:00:34 2020 (r356939)
+++ head/sys/x86/x86/local_apic.c Tue Jan 21 13:22:35 2020 (r356940)
@@ -669,7 +669,8 @@ amd_read_ext_features(void)
{
uint32_t version;
- if (cpu_vendor_id != CPU_VENDOR_AMD)
+ if (cpu_vendor_id != CPU_VENDOR_AMD &&
+ cpu_vendor_id != CPU_VENDOR_HYGON)
return (0);
version = lapic_read32(LAPIC_VERSION);
if ((version & APIC_VER_AMD_EXT_SPACE) != 0)
Modified: head/sys/x86/x86/mca.c
==============================================================================
--- head/sys/x86/x86/mca.c Tue Jan 21 12:00:34 2020 (r356939)
+++ head/sys/x86/x86/mca.c Tue Jan 21 13:22:35 2020 (r356940)
@@ -197,7 +197,8 @@ static int amd_elvt = -1;
static inline bool
amd_thresholding_supported(void)
{
- if (cpu_vendor_id != CPU_VENDOR_AMD)
+ if (cpu_vendor_id != CPU_VENDOR_AMD &&
+ cpu_vendor_id != CPU_VENDOR_HYGON)
return (false);
/*
* The RASCap register is wholly reserved in families 0x10-0x15 (through model 1F).
Modified: head/sys/x86/x86/mp_x86.c
==============================================================================
--- head/sys/x86/x86/mp_x86.c Tue Jan 21 12:00:34 2020 (r356939)
+++ head/sys/x86/x86/mp_x86.c Tue Jan 21 13:22:35 2020 (r356940)
@@ -515,7 +515,8 @@ topo_probe(void)
if (mp_ncpus <= 1)
; /* nothing */
- else if (cpu_vendor_id == CPU_VENDOR_AMD)
+ else if (cpu_vendor_id == CPU_VENDOR_AMD ||
+ cpu_vendor_id == CPU_VENDOR_HYGON)
topo_probe_amd();
else if (cpu_vendor_id == CPU_VENDOR_INTEL)
topo_probe_intel();
Modified: head/sys/x86/x86/msi.c
==============================================================================
--- head/sys/x86/x86/msi.c Tue Jan 21 12:00:34 2020 (r356939)
+++ head/sys/x86/x86/msi.c Tue Jan 21 13:22:35 2020 (r356940)
@@ -321,6 +321,7 @@ msi_init(void)
switch (cpu_vendor_id) {
case CPU_VENDOR_INTEL:
case CPU_VENDOR_AMD:
+ case CPU_VENDOR_HYGON:
break;
case CPU_VENDOR_CENTAUR:
if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
Modified: head/sys/x86/x86/tsc.c
==============================================================================
--- head/sys/x86/x86/tsc.c Tue Jan 21 12:00:34 2020 (r356939)
+++ head/sys/x86/x86/tsc.c Tue Jan 21 13:22:35 2020 (r356940)
@@ -250,6 +250,7 @@ probe_tsc_freq(void)
switch (cpu_vendor_id) {
case CPU_VENDOR_AMD:
+ case CPU_VENDOR_HYGON:
if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 ||
(vm_guest == VM_GUEST_NO &&
CPUID_TO_FAMILY(cpu_id) >= 0x10))
@@ -513,6 +514,7 @@ retry:
if (smp_tsc && tsc_is_invariant) {
switch (cpu_vendor_id) {
case CPU_VENDOR_AMD:
+ case CPU_VENDOR_HYGON:
/*
* Starting with Family 15h processors, TSC clock
* source is in the north bridge. Check whether
@@ -610,7 +612,8 @@ init:
for (shift = 0; shift <= 31 && (tsc_freq >> shift) > max_freq; shift++)
;
if ((cpu_feature & CPUID_SSE2) != 0 && mp_ncpus > 1) {
- if (cpu_vendor_id == CPU_VENDOR_AMD) {
+ if (cpu_vendor_id == CPU_VENDOR_AMD ||
+ cpu_vendor_id == CPU_VENDOR_HYGON) {
tsc_timecounter.tc_get_timecount = shift > 0 ?
tsc_get_timecount_low_mfence :
tsc_get_timecount_mfence;
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