svn commit: r357595 - head/sys/riscv/include

[John Baldwin]

Author: jhb
Date: Wed Feb  5 20:34:22 2020
New Revision: 357595
URL: https://svnweb.freebsd.org/changeset/base/357595

Log:
  Fix EXCP_MASK to include all relevant bits from scause.
  
  While cause codes higher than 16 are reserved, the exception code
  field of the register is defined to be all bits but the upper-most
  bit.
  
  Reviewed by:	mhorne
  MFC after:	1 week
  Sponsored by:	DARPA
  Differential Revision:	https://reviews.freebsd.org/D23510

Modified:
  head/sys/riscv/include/riscvreg.h

Modified: head/sys/riscv/include/riscvreg.h
==============================================================================
--- head/sys/riscv/include/riscvreg.h	Wed Feb  5 20:32:37 2020	(r357594)
+++ head/sys/riscv/include/riscvreg.h	Wed Feb  5 20:34:22 2020	(r357595)
@@ -37,8 +37,7 @@
 #ifndef _MACHINE_RISCVREG_H_
 #define	_MACHINE_RISCVREG_H_
 
-#define	EXCP_SHIFT			0
-#define	EXCP_MASK			(0xf << EXCP_SHIFT)
+#define	EXCP_MASK			(~EXCP_INTR)
 #define	EXCP_MISALIGNED_FETCH		0
 #define	EXCP_FAULT_FETCH		1
 #define	EXCP_ILLEGAL_INSTRUCTION	2