svn commit: r355145 - head/sys/arm64/arm64

[Konstantin Belousov]

On Thu, Nov 28, 2019 at 09:17:15AM +0000, Andrew Turner wrote:
> 
> 
> > On 28 Nov 2019, at 08:48, Michal Meloun <meloun.michal at gmail.com> wrote:
> > 
> > 
> > 
> > On 27.11.2019 21:33, Alan Cox wrote:
> >> Author: alc
> >> Date: Wed Nov 27 20:33:49 2019
> >> New Revision: 355145
> >> URL: https://svnweb.freebsd.org/changeset/base/355145
> >> 
> >> Log:
> >>  There is no reason why we need to pin the underlying thread to its current
> >>  processor in pmap_invalidate_{all,page,range}().  These functions are using
> >>  an instruction that broadcasts the TLB invalidation to every processor, so
> >>  even if a thread migrates in the middle of one of these functions every
> >>  processor will still perform the required TLB invalidations.
> > I think this is not the right assumption. The problem is not in TLB
> > operations themselves, but in following 'dsb' and / or 'isb'. 'dsb'
> > ensures that all TLB operation transmitted by the local CPU is performed
> > and visible to other observers. But it does nothing with TLBs emitted by
> > other CPUs.
> > For example, if a given thread is rescheduled after all TLB operations
> > but before 'dsb' or 'isb' is performed, then the requested
> > synchronization does not occur at all.
> 
> The tibi instructions need a context synchronisation point. One option is the dsb & isb instructions, another is an exception entry.
> 
> For a thread to be rescheduled it requires the timer interrupt to fire. As an exception entry is a context synchronisation point and an interrupt will cause an exception entry there will be such a point after the the tibi instruction.
> 

D5.10.2. TLB maintenance instructions, 'Ordering and completion of
TLB maintenance instructions' states that DSB on the PE that issued
TLBI is required. It does not state that arbitrary even causing
SynchronizeContext() is enough.

Also I was not able to find any explanation of SynchronizeContext().

Curiously, on IA32 exceptions are not specified to issue a serialization
point, although rumors say that on all produced microarchitectures they are.