svn commit: r348349 - in head: lib/libc/net sys/i386/i386

[Pedro F. Giffuni]

Author: pfg
Date: Wed May 29 02:08:23 2019
New Revision: 348349
URL: https://svnweb.freebsd.org/changeset/base/348349

Log:
  typo: suppported.

Modified:
  head/lib/libc/net/rthdr.c
  head/sys/i386/i386/initcpu.c

Modified: head/lib/libc/net/rthdr.c
==============================================================================
--- head/lib/libc/net/rthdr.c	Wed May 29 02:03:08 2019	(r348348)
+++ head/lib/libc/net/rthdr.c	Wed May 29 02:08:23 2019	(r348349)
@@ -282,7 +282,7 @@ inet6_rth_space(int type, int segments)
 			return (((segments * 2) + 1) << 3);
 		/* FALLTHROUGH */
 	default:
-		return (0);	/* type not suppported */
+		return (0);	/* type not supported */
 	}
 }
 

Modified: head/sys/i386/i386/initcpu.c
==============================================================================
--- head/sys/i386/i386/initcpu.c	Wed May 29 02:03:08 2019	(r348348)
+++ head/sys/i386/i386/initcpu.c	Wed May 29 02:08:23 2019	(r348349)
@@ -848,7 +848,7 @@ enable_K6_wt_alloc(void)
 	 */
 	/*
 	 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
-	 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
+	 * but only the Cache Inhibit(CI) (bit 3 of TR12) is supported.
 	 * All other bits in TR12 have no effect on the processer's operation.
 	 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
 	 * on the AMD-K6.
@@ -898,7 +898,7 @@ enable_K6_2_wt_alloc(void)
 	 */
 	/*
 	 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
-	 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
+	 * but only the Cache Inhibit(CI) (bit 3 of TR12) is supported.
 	 * All other bits in TR12 have no effect on the processer's operation.
 	 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
 	 * on the AMD-K6.