svn commit: r347442 - head/sys/arm64/rockchip/clk

[Emmanuel Vadot]

Author: manu
Date: Fri May 10 16:45:17 2019
New Revision: 347442
URL: https://svnweb.freebsd.org/changeset/base/347442

Log:
  arm64: rockchip: Don't always put PLL to normal mode
  
  We used to put every PLL in normal mode (meaning that the output would
  be the result of the PLL configuration) instead of slow mode (the output
  is equal to the external oscillator frequency, 24-26Mhz) but this doesn't
  work for most of the PLLs as when we put them into normal mode the registers
  configuring the output frequency haven't been set.
  Add a normal_mode member in clk_pll_def/clk_pll_sc struct and if it's true
  we then set the PLL to normal mode.
  For now only set it to the LPLL and BPLL (Little cluster PLL and Big cluster
  PLL respectively).
  
  Reviewed by:	ganbold
  Differential Revision:	https://reviews.freebsd.org/D20174

Modified:
  head/sys/arm64/rockchip/clk/rk3399_cru.c
  head/sys/arm64/rockchip/clk/rk_clk_pll.c
  head/sys/arm64/rockchip/clk/rk_clk_pll.h

Modified: head/sys/arm64/rockchip/clk/rk3399_cru.c
==============================================================================
--- head/sys/arm64/rockchip/clk/rk3399_cru.c	Fri May 10 16:44:35 2019	(r347441)
+++ head/sys/arm64/rockchip/clk/rk3399_cru.c	Fri May 10 16:45:17 2019	(r347442)
@@ -764,6 +764,7 @@ static struct rk_clk_pll_def lpll = {
 	.gate_shift = 0,
 	.flags = RK_CLK_PLL_HAVE_GATE,
 	.rates = rk3399_pll_rates,
+	.normal_mode = true,
 };
 
 static struct rk_clk_pll_def bpll = {
@@ -778,6 +779,7 @@ static struct rk_clk_pll_def bpll = {
 	.gate_shift = 1,
 	.flags = RK_CLK_PLL_HAVE_GATE,
 	.rates = rk3399_pll_rates,
+	.normal_mode = true,
 };
 
 static struct rk_clk_pll_def dpll = {

Modified: head/sys/arm64/rockchip/clk/rk_clk_pll.c
==============================================================================
--- head/sys/arm64/rockchip/clk/rk_clk_pll.c	Fri May 10 16:44:35 2019	(r347441)
+++ head/sys/arm64/rockchip/clk/rk_clk_pll.c	Fri May 10 16:45:17 2019	(r347442)
@@ -54,6 +54,8 @@ struct rk_clk_pll_sc {
 
 	struct rk_clk_pll_rate	*rates;
 	struct rk_clk_pll_rate	*frac_rates;
+
+	bool			normal_mode;
 };
 
 #define	WRITE4(_clk, off, val)					\
@@ -344,11 +346,13 @@ rk3399_clk_pll_init(struct clknode *clk, device_t dev)
 
 	sc = clknode_get_softc(clk);
 
-	/* Setting to normal mode */
-	reg = RK3399_CLK_PLL_MODE_NORMAL << RK3399_CLK_PLL_MODE_SHIFT;
-	reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT;
-	WRITE4(clk, sc->base_offset + RK3399_CLK_PLL_MODE_OFFSET,
-	    reg | RK3399_CLK_PLL_WRITE_MASK);
+	if (sc->normal_mode) {
+		/* Setting to normal mode */
+		reg = RK3399_CLK_PLL_MODE_NORMAL << RK3399_CLK_PLL_MODE_SHIFT;
+		reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT;
+		WRITE4(clk, sc->base_offset + RK3399_CLK_PLL_MODE_OFFSET,
+		    reg | RK3399_CLK_PLL_WRITE_MASK);
+	}
 
 	clknode_init_parent_idx(clk, 0);
 
@@ -521,6 +525,7 @@ rk3399_clk_pll_register(struct clkdom *clkdom, struct 
 	sc->flags = clkdef->flags;
 	sc->rates = clkdef->rates;
 	sc->frac_rates = clkdef->frac_rates;
+	sc->normal_mode = clkdef->normal_mode;
 
 	clknode_register(clkdom, clk);
 

Modified: head/sys/arm64/rockchip/clk/rk_clk_pll.h
==============================================================================
--- head/sys/arm64/rockchip/clk/rk_clk_pll.h	Fri May 10 16:44:35 2019	(r347441)
+++ head/sys/arm64/rockchip/clk/rk_clk_pll.h	Fri May 10 16:45:17 2019	(r347442)
@@ -57,6 +57,8 @@ struct rk_clk_pll_def {
 
 	struct rk_clk_pll_rate	*rates;
 	struct rk_clk_pll_rate	*frac_rates;
+
+	bool			normal_mode;
 };
 
 #define	RK_CLK_PLL_HAVE_GATE	0x1