svn commit: r347270 - head/sys/dev/mlx5

[Hans Petter Selasky]

Author: hselasky
Date: Wed May  8 10:39:01 2019
New Revision: 347270
URL: https://svnweb.freebsd.org/changeset/base/347270

Log:
  Expose PCAM, MCAM registers infrastructure in mlx5core.
  
  PCAM: Ports capabilities mask register.
  MCAM: Management capabilities mask register.
  
  PCAM and MCAM registers will provide information regarding firmware
  support for different features, in order to avoid cases where new driver
  combined with old firmware results in syndromes (for ex. PCIe counters
  before this patchset).
  
  Linux commit:
  cfdcbceaeffc669b70d904d80a2df9c86c232566
  
  Submitted by:	slavash@
  MFC after:	3 days
  Sponsored by:	Mellanox Technologies

Modified:
  head/sys/dev/mlx5/device.h
  head/sys/dev/mlx5/driver.h
  head/sys/dev/mlx5/mlx5_ifc.h

Modified: head/sys/dev/mlx5/device.h
==============================================================================
--- head/sys/dev/mlx5/device.h	Wed May  8 10:38:31 2019	(r347269)
+++ head/sys/dev/mlx5/device.h	Wed May  8 10:39:01 2019	(r347270)
@@ -929,6 +929,22 @@ enum mlx5_qcam_feature_groups {
 	MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
 };
 
+enum mlx5_pcam_reg_groups {
+	MLX5_PCAM_REGS_5000_TO_507F = 0x0,
+};
+
+enum mlx5_pcam_feature_groups {
+	MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
+};
+
+enum mlx5_mcam_reg_groups {
+	MLX5_MCAM_REGS_FIRST_128 = 0x0,
+};
+
+enum mlx5_mcam_feature_groups {
+	MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
+};
+
 /* GET Dev Caps macros */
 #define MLX5_CAP_GEN(mdev, cap) \
 	MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)

Modified: head/sys/dev/mlx5/driver.h
==============================================================================
--- head/sys/dev/mlx5/driver.h	Wed May  8 10:38:31 2019	(r347269)
+++ head/sys/dev/mlx5/driver.h	Wed May  8 10:39:01 2019	(r347270)
@@ -149,11 +149,13 @@ enum {
 	MLX5_REG_PELC		 = 0x500e,
 	MLX5_REG_PVLC		 = 0x500f,
 	MLX5_REG_PMLP		 = 0x5002,
+	MLX5_REG_PCAM		 = 0x507f,
 	MLX5_REG_NODE_DESC	 = 0x6001,
 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
 	MLX5_REG_MTMP		 = 0x900a,
 	MLX5_REG_MCIA		 = 0x9014,
 	MLX5_REG_MPCNT		 = 0x9051,
+	MLX5_REG_MCAM		 = 0x907f,
 };
 
 enum dbg_rsc_type {

Modified: head/sys/dev/mlx5/mlx5_ifc.h
==============================================================================
--- head/sys/dev/mlx5/mlx5_ifc.h	Wed May  8 10:38:31 2019	(r347269)
+++ head/sys/dev/mlx5/mlx5_ifc.h	Wed May  8 10:39:01 2019	(r347270)
@@ -1103,7 +1103,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
 	u8         ets[0x1];
 	u8         nic_flow_table[0x1];
 	u8         eswitch_flow_table[0x1];
-	u8         reserved_18[0x3];
+	u8         reserved_18[0x1];
+	u8         mcam_reg[0x1];
+	u8         pcam_reg[0x1];
 	u8         local_ca_ack_delay[0x5];
 	u8         port_module_event[0x1];
 	u8         reserved_19[0x5];
@@ -8544,6 +8546,63 @@ struct mlx5_ifc_qcam_reg_bits {
 		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
 		u8  reserved_at_0[0x80];
 	} qos_feature_cap_mask;
+
+	u8         reserved_at_1c0[0x80];
+};
+
+struct mlx5_ifc_pcam_enhanced_features_bits {
+	u8         reserved_at_0[0x7e];
+
+	u8         ppcnt_discard_group[0x1];
+	u8         ppcnt_statistical_group[0x1];
+};
+
+struct mlx5_ifc_pcam_reg_bits {
+	u8         reserved_at_0[0x8];
+	u8         feature_group[0x8];
+	u8         reserved_at_10[0x8];
+	u8         access_reg_group[0x8];
+
+	u8         reserved_at_20[0x20];
+
+	union {
+		u8         reserved_at_0[0x80];
+	} port_access_reg_cap_mask;
+
+	u8         reserved_at_c0[0x80];
+
+	union {
+		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
+		u8         reserved_at_0[0x80];
+	} feature_cap_mask;
+
+	u8         reserved_at_1c0[0xc0];
+};
+
+struct mlx5_ifc_mcam_enhanced_features_bits {
+	u8         reserved_at_0[0x7f];
+
+	u8         pcie_performance_group[0x1];
+};
+
+struct mlx5_ifc_mcam_reg_bits {
+	u8         reserved_at_0[0x8];
+	u8         feature_group[0x8];
+	u8         reserved_at_10[0x8];
+	u8         access_reg_group[0x8];
+
+	u8         reserved_at_20[0x20];
+
+	union {
+		u8         reserved_at_0[0x80];
+	} mng_access_reg_cap_mask;
+
+	u8         reserved_at_c0[0x80];
+
+	union {
+		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
+		u8         reserved_at_0[0x80];
+	} mng_feature_cap_mask;
 
 	u8         reserved_at_1c0[0x80];
 };