svn commit: r345426 - in head/sys: conf powerpc/aim
Justin Hibbits
jhibbits at FreeBSD.org
Fri Mar 22 22:14:16 UTC 2019
Author: jhibbits
Date: Fri Mar 22 22:14:14 2019
New Revision: 345426
URL: https://svnweb.freebsd.org/changeset/base/345426
Log:
powerpc: Re-merge isa3 HPT with moea64 native HPT
r345402 fixed the bug that led to the split of the ISA 3.0 HPT handling from
the existing manager. The cause of the bug was gcc moving the register
holding VPN to a different register (not r0), which triggered bizarre
behaviors. With the fix, things work, so they can be re-merged. No
performance lost with the merge.
Deleted:
head/sys/powerpc/aim/isa3_hashtb.c
Modified:
head/sys/conf/files.powerpc
head/sys/powerpc/aim/aim_machdep.c
head/sys/powerpc/aim/moea64_native.c
Modified: head/sys/conf/files.powerpc
==============================================================================
--- head/sys/conf/files.powerpc Fri Mar 22 21:31:21 2019 (r345425)
+++ head/sys/conf/files.powerpc Fri Mar 22 22:14:14 2019 (r345426)
@@ -103,7 +103,6 @@ libkern/qdivrem.c optional powerpc | powerpcspe
libkern/ucmpdi2.c optional powerpc | powerpcspe
libkern/udivdi3.c optional powerpc | powerpcspe
libkern/umoddi3.c optional powerpc | powerpcspe
-powerpc/aim/isa3_hashtb.c optional aim powerpc64
powerpc/aim/locore.S optional aim no-obj
powerpc/aim/aim_machdep.c optional aim
powerpc/aim/mmu_oea.c optional aim powerpc
Modified: head/sys/powerpc/aim/aim_machdep.c
==============================================================================
--- head/sys/powerpc/aim/aim_machdep.c Fri Mar 22 21:31:21 2019 (r345425)
+++ head/sys/powerpc/aim/aim_machdep.c Fri Mar 22 22:14:14 2019 (r345426)
@@ -421,9 +421,7 @@ aim_cpu_init(vm_offset_t toc)
* in case the platform module had a better idea of what we
* should do.
*/
- if (cpu_features2 & PPC_FEATURE2_ARCH_3_00)
- pmap_mmu_install(MMU_TYPE_P9H, BUS_PROBE_GENERIC);
- else if (cpu_features & PPC_FEATURE_64)
+ if (cpu_features & PPC_FEATURE_64)
pmap_mmu_install(MMU_TYPE_G5, BUS_PROBE_GENERIC);
else
pmap_mmu_install(MMU_TYPE_OEA, BUS_PROBE_GENERIC);
Modified: head/sys/powerpc/aim/moea64_native.c
==============================================================================
--- head/sys/powerpc/aim/moea64_native.c Fri Mar 22 21:31:21 2019 (r345425)
+++ head/sys/powerpc/aim/moea64_native.c Fri Mar 22 22:14:14 2019 (r345426)
@@ -134,7 +134,8 @@ __FBSDID("$FreeBSD$");
/* POWER9 only permits a 64k partition table size. */
#define PART_SIZE 0x10000
-static int moea64_crop_tlbie;
+static bool moea64_crop_tlbie;
+static bool moea64_need_lock;
static __inline void
TLBIE(uint64_t vpn) {
@@ -149,14 +150,26 @@ TLBIE(uint64_t vpn) {
vpn <<= ADDR_PIDX_SHFT;
/* Hobo spinlock: we need stronger guarantees than mutexes provide */
- while (!atomic_cmpset_int(&tlbie_lock, 0, 1));
- isync(); /* Flush instruction queue once lock acquired */
+ if (moea64_need_lock) {
+ while (!atomic_cmpset_int(&tlbie_lock, 0, 1));
+ isync(); /* Flush instruction queue once lock acquired */
+ }
if (moea64_crop_tlbie)
vpn &= ~(0xffffULL << 48);
#ifdef __powerpc64__
- __asm __volatile("li 0, 0; tlbie %0" :: "r"(vpn) : "0","memory");
+ /*
+ * Explicitly clobber r0. The tlbie instruction has two forms: an old
+ * one used by PowerISA 2.03 and prior, and a newer one used by PowerISA
+ * 2.06 (maybe 2.05?) and later. We need to support both, and it just
+ * so happens that since we use 4k pages we can simply zero out r0, and
+ * clobber it, and the assembler will interpret the single-operand form
+ * of tlbie as having RB set, and everything else as 0. The RS operand
+ * in the newer form is in the same position as the L(page size) bit of
+ * the old form, so a slong as RS is 0, we're good on both sides.
+ */
+ __asm __volatile("li 0, 0 \n tlbie %0" :: "r"(vpn) : "r0", "memory");
__asm __volatile("eieio; tlbsync; ptesync" ::: "memory");
#else
vpn_hi = (uint32_t)(vpn >> 32);
@@ -183,7 +196,8 @@ TLBIE(uint64_t vpn) {
#endif
/* No barriers or special ops -- taken care of by ptesync above */
- tlbie_lock = 0;
+ if (moea64_need_lock)
+ tlbie_lock = 0;
}
#define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR)
@@ -195,6 +209,8 @@ TLBIE(uint64_t vpn) {
static volatile struct lpte *moea64_pteg_table;
static struct rwlock moea64_eviction_lock;
+static volatile struct pate *moea64_part_table;
+
/*
* PTE calls.
*/
@@ -409,9 +425,14 @@ moea64_cpu_bootstrap_native(mmu_t mmup, int ap)
* Install page table
*/
- __asm __volatile ("ptesync; mtsdr1 %0; isync"
- :: "r"(((uintptr_t)moea64_pteg_table & ~DMAP_BASE_ADDRESS)
- | (uintptr_t)(flsl(moea64_pteg_mask >> 11))));
+ if (cpu_features2 & PPC_FEATURE2_ARCH_3_00)
+ mtspr(SPR_PTCR,
+ ((uintptr_t)moea64_part_table & ~DMAP_BASE_ADDRESS) |
+ flsl((PART_SIZE >> 12) - 1));
+ else
+ __asm __volatile ("ptesync; mtsdr1 %0; isync"
+ :: "r"(((uintptr_t)moea64_pteg_table & ~DMAP_BASE_ADDRESS)
+ | (uintptr_t)(flsl(moea64_pteg_mask >> 11))));
tlbia();
}
@@ -427,13 +448,18 @@ moea64_bootstrap_native(mmu_t mmup, vm_offset_t kernel
moea64_early_bootstrap(mmup, kernelstart, kernelend);
switch (mfpvr() >> 16) {
+ case IBMPOWER9:
+ moea64_need_lock = false;
+ break;
case IBMPOWER4:
case IBMPOWER4PLUS:
case IBM970:
case IBM970FX:
case IBM970GX:
case IBM970MP:
- moea64_crop_tlbie = true;
+ moea64_crop_tlbie = true;
+ default:
+ moea64_need_lock = true;
}
/*
* Allocate PTEG table.
@@ -463,9 +489,23 @@ moea64_bootstrap_native(mmu_t mmup, vm_offset_t kernel
if (hw_direct_map)
moea64_pteg_table =
(struct lpte *)PHYS_TO_DMAP((vm_offset_t)moea64_pteg_table);
+ /* Allocate partition table (ISA 3.0). */
+ if (cpu_features2 & PPC_FEATURE2_ARCH_3_00) {
+ moea64_part_table =
+ (struct pate *)moea64_bootstrap_alloc(PART_SIZE, PART_SIZE);
+ if (hw_direct_map)
+ moea64_part_table =
+ (struct pate *)PHYS_TO_DMAP((vm_offset_t)moea64_part_table);
+ }
DISABLE_TRANS(msr);
bzero(__DEVOLATILE(void *, moea64_pteg_table), moea64_pteg_count *
sizeof(struct lpteg));
+ if (cpu_features2 & PPC_FEATURE2_ARCH_3_00) {
+ bzero(__DEVOLATILE(void *, moea64_part_table), PART_SIZE);
+ moea64_part_table[0].pagetab =
+ (DMAP_TO_PHYS((vm_offset_t)moea64_pteg_table)) |
+ (uintptr_t)(flsl((moea64_pteg_count - 1) >> 11));
+ }
ENABLE_TRANS(msr);
CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table);
@@ -512,7 +552,7 @@ tlbia(void)
TLBSYNC();
- for (; i < 0x200000; i += 0x00001000) {
+ for (; i < 0x400000; i += 0x00001000) {
#ifdef __powerpc64__
__asm __volatile("tlbiel %0" :: "r"(i));
#else
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