svn commit: r349482 - in head/contrib/elftoolchain: common readelf
Mitchell Horne
mhorne at FreeBSD.org
Fri Jun 28 00:10:28 UTC 2019
Author: mhorne
Date: Fri Jun 28 00:10:26 2019
New Revision: 349482
URL: https://svnweb.freebsd.org/changeset/base/349482
Log:
readelf: Add support for RISC-V specific e_flags
Reviewed by: markj
Approved by: markj (mentor)
MFC after: 3 days
Differential Revision: https://reviews.freebsd.org/D20767
Modified:
head/contrib/elftoolchain/common/elfdefinitions.h
head/contrib/elftoolchain/readelf/readelf.c
Modified: head/contrib/elftoolchain/common/elfdefinitions.h
==============================================================================
--- head/contrib/elftoolchain/common/elfdefinitions.h Fri Jun 28 00:03:29 2019 (r349481)
+++ head/contrib/elftoolchain/common/elfdefinitions.h Fri Jun 28 00:10:26 2019 (r349482)
@@ -33,7 +33,7 @@
* See: http://www.sco.com/developers/gabi/latest/ch4.intro.html
* - The May 1998 (version 1.5) draft of "The ELF-64 object format".
* - Processor-specific ELF ABI definitions for sparc, i386, amd64, mips,
- * ia64, and powerpc processors.
+ * ia64, powerpc, and RISC-V processors.
* - The "Linkers and Libraries Guide", from Sun Microsystems.
*/
@@ -426,6 +426,22 @@ _ELF_DEFINE_EF(EF_PPC_RELOCATABLE, 0x00010000UL, \
"-mrelocatable flag") \
_ELF_DEFINE_EF(EF_PPC_RELOCATABLE_LIB, 0x00008000UL, \
"-mrelocatable-lib flag") \
+_ELF_DEFINE_EF(EF_RISCV_RVC, 0x00000001UL, \
+ "Compressed instruction extension") \
+_ELF_DEFINE_EF(EF_RISCV_FLOAT_ABI_MASK, 0x00000006UL, \
+ "Floating point ABI") \
+_ELF_DEFINE_EF(EF_RISCV_FLOAT_ABI_SOFT, 0x00000000UL, \
+ "Software emulated floating point") \
+_ELF_DEFINE_EF(EF_RISCV_FLOAT_ABI_SINGLE, 0x00000002UL, \
+ "Single precision floating point") \
+_ELF_DEFINE_EF(EF_RISCV_FLOAT_ABI_DOUBLE, 0x00000004UL, \
+ "Double precision floating point") \
+_ELF_DEFINE_EF(EF_RISCV_FLOAT_ABI_QUAD, 0x00000006UL, \
+ "Quad precision floating point") \
+_ELF_DEFINE_EF(EF_RISCV_RVE, 0x00000008UL, \
+ "Compressed instruction ABI") \
+_ELF_DEFINE_EF(EF_RISCV_TSO, 0x00000010UL, \
+ "RVTSO memory consistency model") \
_ELF_DEFINE_EF(EF_SPARC_EXT_MASK, 0x00ffff00UL, \
"Vendor Extension mask") \
_ELF_DEFINE_EF(EF_SPARC_32PLUS, 0x00000100UL, \
Modified: head/contrib/elftoolchain/readelf/readelf.c
==============================================================================
--- head/contrib/elftoolchain/readelf/readelf.c Fri Jun 28 00:03:29 2019 (r349481)
+++ head/contrib/elftoolchain/readelf/readelf.c Fri Jun 28 00:10:26 2019 (r349482)
@@ -431,6 +431,13 @@ static struct eflags_desc powerpc_eflags_desc[] = {
{0, NULL}
};
+static struct eflags_desc riscv_eflags_desc[] = {
+ {EF_RISCV_RVC, "RVC"},
+ {EF_RISCV_RVE, "RVE"},
+ {EF_RISCV_TSO, "TSO"},
+ {0, NULL}
+};
+
static struct eflags_desc sparc_eflags_desc[] = {
{EF_SPARC_32PLUS, "v8+"},
{EF_SPARC_SUN_US1, "ultrasparcI"},
@@ -2293,6 +2300,23 @@ dump_eflags(struct readelf *re, uint64_t e_flags)
case EM_PPC:
case EM_PPC64:
edesc = powerpc_eflags_desc;
+ break;
+ case EM_RISCV:
+ switch (e_flags & EF_RISCV_FLOAT_ABI_MASK) {
+ case EF_RISCV_FLOAT_ABI_SOFT:
+ printf(", soft-float ABI");
+ break;
+ case EF_RISCV_FLOAT_ABI_SINGLE:
+ printf(", single-float ABI");
+ break;
+ case EF_RISCV_FLOAT_ABI_DOUBLE:
+ printf(", double-float ABI");
+ break;
+ case EF_RISCV_FLOAT_ABI_QUAD:
+ printf(", quad-float ABI");
+ break;
+ }
+ edesc = riscv_eflags_desc;
break;
case EM_SPARC:
case EM_SPARC32PLUS:
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