svn commit: r348685 - in stable/12/sys: conf powerpc/aim powerpc/powerpc
Leandro Lupori
luporl at FreeBSD.org
Wed Jun 5 12:43:47 UTC 2019
Author: luporl
Date: Wed Jun 5 12:43:45 2019
New Revision: 348685
URL: https://svnweb.freebsd.org/changeset/base/348685
Log:
MFC r348112:
Fix PPC64 kernel build with clang8 + lld8
This patch fixes the following lld link errors:
- unsupported dynamic relocations on read-only sections
- out-of-range TOC references
Submitted by: git_bdragon.rtk0.net
Reviewed by: jhibbits, luporl
Differential Revision: https://reviews.freebsd.org/D19352
Modified:
stable/12/sys/conf/ldscript.powerpc64
stable/12/sys/powerpc/aim/trap_subr64.S
stable/12/sys/powerpc/powerpc/cpu_subr64.S
Directory Properties:
stable/12/ (props changed)
Modified: stable/12/sys/conf/ldscript.powerpc64
==============================================================================
--- stable/12/sys/conf/ldscript.powerpc64 Wed Jun 5 12:38:58 2019 (r348684)
+++ stable/12/sys/conf/ldscript.powerpc64 Wed Jun 5 12:43:45 2019 (r348685)
@@ -93,7 +93,8 @@ SECTIONS
.opd : ALIGN(8) { KEEP (*(.opd)) }
.branch_lt : ALIGN(8) { *(.branch_lt) }
. = ALIGN(4096);
- .got : ALIGN(8) { __tocbase = .; *(.got .toc) }
+ .got : ALIGN(8) { __tocbase = .; *(.got) }
+ .toc : ALIGN(8) { *(.toc) }
.dynamic : { *(.dynamic) }
/* Put .ctors and .dtors next to the .got2 section, so that the pointers
Modified: stable/12/sys/powerpc/aim/trap_subr64.S
==============================================================================
--- stable/12/sys/powerpc/aim/trap_subr64.S Wed Jun 5 12:38:58 2019 (r348684)
+++ stable/12/sys/powerpc/aim/trap_subr64.S Wed Jun 5 12:43:45 2019 (r348685)
@@ -317,29 +317,33 @@ CNAME(rstcode):
* processor is waking up from power saving mode
* It is software reset when 46:47 = 0b00
*/
+ /* 0x00 */
+ ld %r2,TRAP_GENTRAP(0) /* Real-mode &generictrap */
mfsrr1 %r9 /* Load SRR1 into r9 */
andis. %r9,%r9,0x3 /* Logic AND with 46:47 bits */
+
beq 2f /* Branch if software reset */
- bl 1f
- .llong cpu_wakeup_handler
+ /* 0x10 */
+ /* Reset was wakeup */
+ addi %r9,%r2,(cpu_wakeup_handler-generictrap)
+ b 1f /* Was power save, do the wakeup */
- /* It is software reset */
-
+ /* Reset was software reset */
/* Explicitly set MSR[SF] */
2: mfmsr %r9
li %r8,1
+ /* 0x20 */
insrdi %r9,%r8,1,0
mtmsrd %r9
isync
- bl 1f
- .llong cpu_reset_handler /* Make sure to maintain 8-byte alignment */
+ addi %r9,%r2,(cpu_reset_handler-generictrap)
-1: mflr %r9
- ld %r9,0(%r9)
- mtlr %r9
-
- blr
+ /* 0x30 */
+1: mtlr %r9
+ blr /* Branch to either cpu_reset_handler
+ * or cpu_wakeup_handler.
+ */
CNAME(rstcodeend):
cpu_reset_handler:
@@ -457,52 +461,59 @@ CNAME(hypertrapcode):
addi %r1,%r1,(generichypertrap-generictrap)
mtlr %r1
li %r1, 0xe0 /* How to get the vector from LR */
- blrl /* Branch to generictrap */
+ blrl /* Branch to generichypertrap */
CNAME(hypertrapcodeend):
/*
* For SLB misses: do special things for the kernel
*
- * Note: SPRG1 is always safe to overwrite any time the MMU is on, which is
+ * Note: SPRG1 is always safe to overwrite any time the MMU was on, which is
* the only time this can be called.
*/
.globl CNAME(slbtrap),CNAME(slbtrapend)
.p2align 3
CNAME(slbtrap):
+ /* 0x00 */
mtsprg1 %r1 /* save SP */
GET_CPUINFO(%r1)
- std %r2,(PC_SLBSAVE+16)(%r1)
- mfcr %r2 /* save CR */
- std %r2,(PC_SLBSAVE+104)(%r1)
+ std %r2,(PC_SLBSAVE+16)(%r1) /* save r2 */
+ mfcr %r2
+ /* 0x10 */
+ std %r2,(PC_SLBSAVE+104)(%r1) /* save CR */
mfsrr1 %r2 /* test kernel mode */
mtcr %r2
bf 17,2f /* branch if PSL_PR is false */
+ /* 0x20 */
/* User mode */
- ld %r2,(PC_SLBSAVE+104)(%r1) /* Restore CR */
- mtcr %r2
- ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore R2 */
- mflr %r1 /* Save the old LR in r1 */
- mtsprg2 %r1 /* And then in SPRG2 */
- /* 52 bytes so far */
- bl 1f
- .llong generictrap
-1: mflr %r1
- ld %r1,0(%r1)
+ ld %r2,(PC_SLBSAVE+104)(%r1)
+ mtcr %r2 /* restore CR */
+ ld %r2,(PC_SLBSAVE+16)(%r1) /* restore r2 */
+ mflr %r1
+ /* 0x30 */
+ mtsprg2 %r1 /* save LR in SPRG2 */
+ ld %r1,TRAP_GENTRAP(0) /* real-mode &generictrap */
mtlr %r1
li %r1, 0x80 /* How to get the vector from LR */
+ /* 0x40 */
blrl /* Branch to generictrap */
- /* 84 bytes */
2: mflr %r2 /* Save the old LR in r2 */
- nop
- bl 3f /* Begin dance to jump to kern_slbtrap*/
- .llong kern_slbtrap
-3: mflr %r1
- ld %r1,0(%r1)
+ /* Kernel mode */
+ ld %r1,TRAP_GENTRAP(0) /* Real-mode &generictrap */
+ addi %r1,%r1,(kern_slbtrap-generictrap)
+ /* 0x50 */
mtlr %r1
GET_CPUINFO(%r1)
- blrl /* 124 bytes -- 4 to spare */
+ blrl /* Branch to kern_slbtrap */
+/* must fit in 128 bytes! */
CNAME(slbtrapend):
+/*
+ * On entry:
+ * SPRG1: SP
+ * r1: pcpu
+ * r2: LR
+ * LR: branch address in trap region
+ */
kern_slbtrap:
std %r2,(PC_SLBSAVE+136)(%r1) /* old LR */
std %r3,(PC_SLBSAVE+24)(%r1) /* save R3 */
@@ -510,7 +521,7 @@ kern_slbtrap:
/* Check if this needs to be handled as a regular trap (userseg miss) */
mflr %r2
andi. %r2,%r2,0xff80
- cmpwi %r2,0x380
+ cmpwi %r2,EXC_DSE
bne 1f
mfdar %r2
b 2f
@@ -639,14 +650,8 @@ CNAME(alitrap):
mflr %r28 /* save LR */
mfcr %r29 /* save CR */
- /* Begin dance to branch to s_trap in a bit */
- b 1f
- .p2align 3
-1: nop
- bl 1f
- .llong s_trap
-1: mflr %r31
- ld %r31,0(%r31)
+ ld %r31,TRAP_GENTRAP(0)
+ addi %r31,%r31,(s_trap - generictrap)
mtlr %r31
/* Put our exception vector in SPRG3 */
@@ -656,7 +661,7 @@ CNAME(alitrap):
/* Test whether we already had PR set */
mfsrr1 %r31
mtcr %r31
- blrl
+ blrl /* Branch to s_trap */
CNAME(aliend):
/*
@@ -679,12 +684,10 @@ CNAME(dsitrap):
mfsrr1 %r31 /* test kernel mode */
mtcr %r31
mflr %r28 /* save LR (SP already saved) */
- bl 1f /* Begin branching to disitrap */
- .llong disitrap
-1: mflr %r1
- ld %r1,0(%r1)
+ ld %r1,TRAP_GENTRAP(0)
+ addi %r1,%r1,(disitrap-generictrap)
mtlr %r1
- blrl /* Branch to generictrap */
+ blrl /* Branch to disitrap */
CNAME(dsiend):
/*
@@ -953,7 +956,7 @@ CNAME(dblow):
mtlr %r1
li %r1, 0 /* How to get the vector from LR */
blrl /* Branch to generictrap */
-
+ /* No fallthrough */
1:
GET_CPUINFO(%r1)
std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r1) /* free r27 */
@@ -963,12 +966,9 @@ CNAME(dblow):
std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */
std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */
mflr %r28 /* save LR */
- nop /* alignment */
- bl 9f /* Begin branch */
- .llong dbtrap
-9: mflr %r1
- ld %r1,0(%r1)
+ ld %r1,TRAP_GENTRAP(0)
+ addi %r1,%r1,(dbtrap-generictrap)
mtlr %r1
- blrl /* Branch to generictrap */
+ blrl /* Branch to dbtrap */
CNAME(dbend):
#endif /* KDB */
Modified: stable/12/sys/powerpc/powerpc/cpu_subr64.S
==============================================================================
--- stable/12/sys/powerpc/powerpc/cpu_subr64.S Wed Jun 5 12:38:58 2019 (r348684)
+++ stable/12/sys/powerpc/powerpc/cpu_subr64.S Wed Jun 5 12:43:45 2019 (r348685)
@@ -31,7 +31,6 @@
#include <machine/asm.h>
- .globl CNAME(power_save_sequence)
.p2align 3
ENTRY(enter_idle_powerx)
mfsprg0 %r3 /* Get the pcpu pointer */
@@ -65,11 +64,9 @@ ENTRY(enter_idle_powerx)
std %r1,PCB_SP(%r3) /* Save the stack pointer */
std %r2,PCB_TOC(%r3) /* Save the TOC pointer */
- /* Set where we want to jump */
bl 1f
- .llong power_save_sequence /* Remember about 8 byte alignment */
1: mflr %r3
- ld %r3,0(%r3)
+ addi %r3,%r3,power_save_sequence-1b
mtsrr0 %r3
/* Set MSR */
@@ -82,7 +79,7 @@ ENTRY(enter_idle_powerx)
rfid
.p2align 2
-CNAME(power_save_sequence):
+power_save_sequence:
bl 1f
.llong 0x0 /* Playground for power-save sequence */
1: mflr %r3
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