svn commit: r350242 - head/sys/arm64/include
Andrew Turner
andrew at FreeBSD.org
Tue Jul 23 14:52:47 UTC 2019
Author: andrew
Date: Tue Jul 23 14:52:46 2019
New Revision: 350242
URL: https://svnweb.freebsd.org/changeset/base/350242
Log:
As with r350241 use the new UL macro on the main register mask.
MFC after: 1 week
Sponsored by: DARPA, AFRL
Modified:
head/sys/arm64/include/armreg.h
Modified: head/sys/arm64/include/armreg.h
==============================================================================
--- head/sys/arm64/include/armreg.h Tue Jul 23 14:40:37 2019 (r350241)
+++ head/sys/arm64/include/armreg.h Tue Jul 23 14:52:46 2019 (r350242)
@@ -176,7 +176,7 @@
#define ICC_SRE_EL2_EN (1U << 3)
/* ID_AA64DFR0_EL1 */
-#define ID_AA64DFR0_MASK 0x0000000ff0f0fffful
+#define ID_AA64DFR0_MASK UL(0x0000000ff0f0ffff)
#define ID_AA64DFR0_DebugVer_SHIFT 0
#define ID_AA64DFR0_DebugVer_MASK (UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT)
#define ID_AA64DFR0_DebugVer(x) ((x) & ID_AA64DFR0_DebugVer_MASK)
@@ -214,7 +214,7 @@
#define ID_AA64DFR0_PMSVer_V1 (UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT)
/* ID_AA64ISAR0_EL1 */
-#define ID_AA64ISAR0_MASK 0x0000fffff0fffff0ul
+#define ID_AA64ISAR0_MASK UL(0x0000fffff0fffff0)
#define ID_AA64ISAR0_AES_SHIFT 4
#define ID_AA64ISAR0_AES_MASK (UL(0xf) << ID_AA64ISAR0_AES_SHIFT)
#define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK)
@@ -269,7 +269,7 @@
#define ID_AA64ISAR0_DP_IMPL (UL(0x1) << ID_AA64ISAR0_DP_SHIFT)
/* ID_AA64ISAR1_EL1 */
-#define ID_AA64ISAR1_MASK 0xffffffff
+#define ID_AA64ISAR1_MASK UL(0x00000000ffffffff)
#define ID_AA64ISAR1_DPB_SHIFT 0
#define ID_AA64ISAR1_DPB_MASK (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_DPB(x) ((x) & ID_AA64ISAR1_DPB_MASK)
@@ -312,7 +312,7 @@
#define ID_AA64ISAR1_GPI_IMPL (UL(0x1) << ID_AA64ISAR1_GPI_SHIFT)
/* ID_AA64MMFR0_EL1 */
-#define ID_AA64MMFR0_MASK 0xffffffff
+#define ID_AA64MMFR0_MASK UL(0x00000000ffffffff)
#define ID_AA64MMFR0_PARange_SHIFT 0
#define ID_AA64MMFR0_PARange_MASK (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT)
#define ID_AA64MMFR0_PARange(x) ((x) & ID_AA64MMFR0_PARange_MASK)
@@ -360,7 +360,7 @@
#define ID_AA64MMFR0_TGran4_NONE (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
/* ID_AA64MMFR1_EL1 */
-#define ID_AA64MMFR1_MASK 0xffffffff
+#define ID_AA64MMFR1_MASK UL(0x00000000ffffffff)
#define ID_AA64MMFR1_HAFDBS_SHIFT 0
#define ID_AA64MMFR1_HAFDBS_MASK (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT)
#define ID_AA64MMFR1_HAFDBS(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK)
@@ -407,7 +407,7 @@
/* ID_AA64MMFR2_EL1 */
#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
-#define ID_AA64MMFR2_MASK 0x0fffffff
+#define ID_AA64MMFR2_MASK UL(0x000000000fffffff)
#define ID_AA64MMFR2_CnP_SHIFT 0
#define ID_AA64MMFR2_CnP_MASK (UL(0xf) << ID_AA64MMFR2_CnP_SHIFT)
#define ID_AA64MMFR2_CnP(x) ((x) & ID_AA64MMFR2_CnP_MASK)
@@ -445,7 +445,7 @@
#define ID_AA64MMFR2_NV_IMPL (UL(0x1) << ID_AA64MMFR2_NV_SHIFT)
/* ID_AA64PFR0_EL1 */
-#define ID_AA64PFR0_MASK 0x0000000ffffffffful
+#define ID_AA64PFR0_MASK UL(0x0000000fffffffff)
#define ID_AA64PFR0_EL0_SHIFT 0
#define ID_AA64PFR0_EL0_MASK (UL(0xf) << ID_AA64PFR0_EL0_SHIFT)
#define ID_AA64PFR0_EL0(x) ((x) & ID_AA64PFR0_EL0_MASK)
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