svn commit: r344056 - in head/contrib/llvm: include/llvm/CodeGen lib/CodeGen/SelectionDAG lib/Target/AArch64 lib/Target/ARM
Dimitry Andric
dim at FreeBSD.org
Tue Feb 12 18:32:16 UTC 2019
Author: dim
Date: Tue Feb 12 18:32:14 2019
New Revision: 344056
URL: https://svnweb.freebsd.org/changeset/base/344056
Log:
Pull in r339734 from upstream llvm trunk (by Eli Friedman):
[ARM] Make PerformSHLSimplify add nodes to the DAG worklist correctly.
Intentionally excluding nodes from the DAGCombine worklist is likely
to lead to weird optimizations and infinite loops, so it's generally
a bad idea.
To avoid the infinite loops, fix DAGCombine to use the
isDesirableToCommuteWithShift target hook before performing the
transforms in question, and implement the target hook in the ARM
backend disable the transforms in question.
Fixes https://bugs.llvm.org/show_bug.cgi?id=38530 . (I don't have a
reduced testcase for that bug. But we should have sufficient test
coverage for PerformSHLSimplify given that we're not playing weird
tricks with the worklist. I can try to bugpoint it if necessary,
though.)
Differential Revision: https://reviews.llvm.org/D50667
This should fix a possible hang when compiling sys/dev/nxge/if_nxge.c
(which exists now only in the stable/11 branch) for arm.
Modified:
head/contrib/llvm/include/llvm/CodeGen/TargetLowering.h
head/contrib/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.h
head/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp
head/contrib/llvm/lib/Target/ARM/ARMISelLowering.h
Modified: head/contrib/llvm/include/llvm/CodeGen/TargetLowering.h
==============================================================================
--- head/contrib/llvm/include/llvm/CodeGen/TargetLowering.h Tue Feb 12 17:07:15 2019 (r344055)
+++ head/contrib/llvm/include/llvm/CodeGen/TargetLowering.h Tue Feb 12 18:32:14 2019 (r344056)
@@ -2935,12 +2935,16 @@ class TargetLowering : public TargetLoweringBase { (pu
///
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
- /// Return true if it is profitable to move a following shift through this
- // node, adjusting any immediate operands as necessary to preserve semantics.
- // This transformation may not be desirable if it disrupts a particularly
- // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
- // By default, it returns true.
- virtual bool isDesirableToCommuteWithShift(const SDNode *N) const {
+ /// Return true if it is profitable to move this shift by a constant amount
+ /// though its operand, adjusting any immediate operands as necessary to
+ /// preserve semantics. This transformation may not be desirable if it
+ /// disrupts a particularly auspicious target-specific tree (e.g. bitfield
+ /// extraction in AArch64). By default, it returns true.
+ ///
+ /// @param N the shift node
+ /// @param Level the current DAGCombine legalization level.
+ virtual bool isDesirableToCommuteWithShift(const SDNode *N,
+ CombineLevel Level) const {
return true;
}
Modified: head/contrib/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
==============================================================================
--- head/contrib/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Feb 12 17:07:15 2019 (r344055)
+++ head/contrib/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Feb 12 18:32:14 2019 (r344056)
@@ -6191,7 +6191,7 @@ SDValue DAGCombiner::visitShiftByConstant(SDNode *N, C
return SDValue();
}
- if (!TLI.isDesirableToCommuteWithShift(LHS))
+ if (!TLI.isDesirableToCommuteWithShift(N, Level))
return SDValue();
// Fold the constants, shifting the binop RHS by the shift amount.
@@ -6495,7 +6495,8 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR) &&
N0.getNode()->hasOneUse() &&
isConstantOrConstantVector(N1, /* No Opaques */ true) &&
- isConstantOrConstantVector(N0.getOperand(1), /* No Opaques */ true)) {
+ isConstantOrConstantVector(N0.getOperand(1), /* No Opaques */ true) &&
+ TLI.isDesirableToCommuteWithShift(N, Level)) {
SDValue Shl0 = DAG.getNode(ISD::SHL, SDLoc(N0), VT, N0.getOperand(0), N1);
SDValue Shl1 = DAG.getNode(ISD::SHL, SDLoc(N1), VT, N0.getOperand(1), N1);
AddToWorklist(Shl0.getNode());
Modified: head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Feb 12 17:07:15 2019 (r344055)
+++ head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Feb 12 18:32:14 2019 (r344056)
@@ -8496,7 +8496,9 @@ AArch64TargetLowering::getScratchRegisters(CallingConv
}
bool
-AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
+AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N,
+ CombineLevel Level) const {
+ N = N->getOperand(0).getNode();
EVT VT = N->getValueType(0);
// If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
// it with shift to let it be lowered to UBFX.
Modified: head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.h
==============================================================================
--- head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.h Tue Feb 12 17:07:15 2019 (r344055)
+++ head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.h Tue Feb 12 18:32:14 2019 (r344056)
@@ -363,7 +363,8 @@ class AArch64TargetLowering : public TargetLowering {
const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
/// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
- bool isDesirableToCommuteWithShift(const SDNode *N) const override;
+ bool isDesirableToCommuteWithShift(const SDNode *N,
+ CombineLevel Level) const override;
/// Returns true if it is beneficial to convert a load of a constant
/// to just the constant itself.
Modified: head/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp Tue Feb 12 17:07:15 2019 (r344055)
+++ head/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp Tue Feb 12 18:32:14 2019 (r344056)
@@ -10407,6 +10407,25 @@ static SDValue PerformADDCombineWithOperands(SDNode *N
return SDValue();
}
+bool
+ARMTargetLowering::isDesirableToCommuteWithShift(const SDNode *N,
+ CombineLevel Level) const {
+ if (Level == BeforeLegalizeTypes)
+ return true;
+
+ if (Subtarget->isThumb() && Subtarget->isThumb1Only())
+ return true;
+
+ if (N->getOpcode() != ISD::SHL)
+ return true;
+
+ // Turn off commute-with-shift transform after legalization, so it doesn't
+ // conflict with PerformSHLSimplify. (We could try to detect when
+ // PerformSHLSimplify would trigger more precisely, but it isn't
+ // really necessary.)
+ return false;
+}
+
static SDValue PerformSHLSimplify(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI,
const ARMSubtarget *ST) {
@@ -10506,9 +10525,7 @@ static SDValue PerformSHLSimplify(SDNode *N,
LLVM_DEBUG(dbgs() << "Simplify shl use:\n"; SHL.getOperand(0).dump();
SHL.dump(); N->dump());
LLVM_DEBUG(dbgs() << "Into:\n"; X.dump(); BinOp.dump(); Res.dump());
-
- DAG.ReplaceAllUsesWith(SDValue(N, 0), Res);
- return SDValue(N, 0);
+ return Res;
}
Modified: head/contrib/llvm/lib/Target/ARM/ARMISelLowering.h
==============================================================================
--- head/contrib/llvm/lib/Target/ARM/ARMISelLowering.h Tue Feb 12 17:07:15 2019 (r344055)
+++ head/contrib/llvm/lib/Target/ARM/ARMISelLowering.h Tue Feb 12 18:32:14 2019 (r344056)
@@ -583,6 +583,9 @@ class VectorType;
unsigned getABIAlignmentForCallingConv(Type *ArgTy,
DataLayout DL) const override;
+ bool isDesirableToCommuteWithShift(const SDNode *N,
+ CombineLevel Level) const override;
+
protected:
std::pair<const TargetRegisterClass *, uint8_t>
findRepresentativeClass(const TargetRegisterInfo *TRI,
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