svn commit: r343876 - head/sys/arm64/arm64

Andrew Turner andrew at
Thu Feb 7 20:58:46 UTC 2019

Author: andrew
Date: Thu Feb  7 20:58:45 2019
New Revision: 343876

  Add missing data barriers after storeing a new valid pagetable entry.
  When moving from an invalid to a valid entry we don't need to invalidate
  the tlb, however we do need to ensure the store is ordered before later
  memory accesses. This is because this later access may be to a virtual
  address within the newly mapped region.
  Add the needed barriers to places where we don't later invalidate the
  tlb. When we do invalidate the tlb there will be a barrier to correctly
  order this.
  This fixes a panic on boot on ThunderX2 when INVARIANTS is turned off:
  panic: vm_fault_hold: fault on nofault entry, addr: 0xffff000040c11000
  Reported by:	jchandra
  Tested by:	jchandra
  Sponsored by:	DARPA, AFRL
  Differential Revision:


Modified: head/sys/arm64/arm64/pmap.c
--- head/sys/arm64/arm64/pmap.c	Thu Feb  7 20:50:39 2019	(r343875)
+++ head/sys/arm64/arm64/pmap.c	Thu Feb  7 20:58:45 2019	(r343876)
@@ -2862,6 +2862,7 @@ pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_ent
 	/* Create the new mapping */
 	pmap_load_store(pte, newpte);
+	dsb(ishst);
@@ -3281,6 +3282,7 @@ validate:
 	} else {
 		/* New mappig */
 		pmap_load_store(l3, new_l3);
+		dsb(ishst);
@@ -3435,6 +3437,7 @@ pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t 
 	 * Map the superpage.
 	(void)pmap_load_store(l2, new_l2);
+	dsb(ishst);
 	atomic_add_long(&pmap_l2_mappings, 1);
 	CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",

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