svn commit: r355427 - head/sys/arm64/arm64

[Alan Cox]

Author: alc
Date: Thu Dec  5 19:25:49 2019
New Revision: 355427
URL: https://svnweb.freebsd.org/changeset/base/355427

Log:
  On a context switch, handle the possibility that the old thread was
  preempted after an "ic" or "tlbi" instruction but before it performed a
  "dsb" instruction.  The "ic" and "tlbi" instructions have unusual
  synchronization requirements.  If the old thread migrates to a new
  processor, its completion of a "dsb" instruction on that new processor does
  not guarantee that the "ic" or "tlbi" instructions performed on the old
  processor have completed.
  
  This issue is not restricted to the kernel.  Since locore.S sets the UCI bit
  in SCTLR, user-space programs can perform "ic ivau" instructions (as well as
  some forms of the "dc" instruction).
  
  Reviewed by:	andrew, kib, markj, mmel
  X-MFC with:	r355145
  Differential Revision:	https://reviews.freebsd.org/D22622

Modified:
  head/sys/arm64/arm64/pmap.c

Modified: head/sys/arm64/arm64/pmap.c
==============================================================================
--- head/sys/arm64/arm64/pmap.c	Thu Dec  5 18:47:29 2019	(r355426)
+++ head/sys/arm64/arm64/pmap.c	Thu Dec  5 19:25:49 2019	(r355427)
@@ -5850,8 +5850,18 @@ pmap_activate_int(pmap_t pmap)
 
 	KASSERT(PCPU_GET(curpmap) != NULL, ("no active pmap"));
 	KASSERT(pmap != kernel_pmap, ("kernel pmap activation"));
-	if (pmap == PCPU_GET(curpmap))
+	if (pmap == PCPU_GET(curpmap)) {
+		/*
+		 * Handle the possibility that the old thread was preempted
+		 * after an "ic" or "tlbi" instruction but before it performed
+		 * a "dsb" instruction.  If the old thread migrates to a new
+		 * processor, its completion of a "dsb" instruction on that
+		 * new processor does not guarantee that the "ic" or "tlbi"
+		 * instructions performed on the old processor have completed.
+		 */
+		dsb(ish);
 		return (false);
+	}
 
 	/*
 	 * Ensure that the store to curpmap is globally visible before the