svn commit: r346598 - head/sys/modules

[Ganbold Tsagaankhuu]

On Mon, Apr 29, 2019 at 11:16 PM Andrew Gallatin <gallatin at cs.duke.edu>
wrote:

> On 2019-04-29 10:54, Emmanuel Vadot wrote:
> > On Mon, 29 Apr 2019 10:49:01 -0400
> > Andrew Gallatin <gallatin at cs.duke.edu> wrote:
> >
> >> On 2019-04-29 10:21, Rodney W. Grimes wrote:
> >>>> On Tue, 23 Apr 2019 at 13:26, Rodney W. Grimes
> >>>> <freebsd at gndrsh.dnsmgr.net> wrote:
> >>>>>
> >>>>> Very cool, now how do I get a PCIe slot into a RPI3!!! lol  :-)
> >>>>
> >>>> I know you're joking but the comment does highlight an issue in the
> >>>> AArch64 world - there's a lack of good mid-range developer platforms.
> >>>
> >>> I may of been joking with respect to the RPI3, but at the same
> >>> time I do know that the RockPro64 exists and does have that
> >>> PCIe slot I want, I also know that Michael Dexter has one he would
> >>> loan me should I wish to investigate our state of support.
> >>
> >> Does anybody know what PCIe Generation / speed that slot runs at?
> >> All I can find them saying is "PCIe x4", which implies Gen 1, 2.5GT/s
> >> speeds, which is not terribly useful.  Gen2 or better would be enough
> >> to run 10GbE, which would be fun :)
> >>
> >> Drew
> >
> >   It/s PCIe 2.1 compatible. See
> > http://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf
> >
>
> Everything I'm seeing there says Gen1 vs Gen2 depends on
> "PCIE_GENERATION_SEL", and that if its set to 0, you get
> Gen1 2.5Gt/s and if it is set to 1, you get Gen2, 5.0Gt/s.
> But I don't see anything specifying this value for the
> RockPro64 board.
>

If you check Rockchip RK3399 TRM V1.3 Part1.pdf
<http://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part1.pdf> you can see
PCIe 2.1 in block diagram  (Fig 1-1)

Ganbold



>
> Drew
>
>