svn commit: r346593 - head/sys/sys

[Mark Johnston]

On Thu, Apr 25, 2019 at 11:22:22AM +0300, Konstantin Belousov wrote:
> On Thu, Apr 25, 2019 at 07:38:21AM +0200, Wojciech Macek wrote:
> > Intel does not reorder reads against the condition "if" here. I know for
> > sure that ARM does, but therestill might be some other architectures that
> > also suffers such behavior - I just don't have any means to verify.
> > I remember the discussion for rS302292 where we agreed that this kind of
> > patches should be the least impacting in perfomrance as possible. Adding
> > unconditional memory barrier causes significant performance drop on Intel,
> > where in fact, the issue was never seen.
> > 
> Atomic_thread_fence_acq() is nop on x86, or rather, it is compiler memory
> barrier.  If you need read/read fence on some architectures, I am sure
> that you need compiler barrier on all.

To add a bit, one reason to prefer atomic(9) to explicit fences is
precisely because it issues fences only when required by a given
CPU architecture.  There is no "unconditional memory barrier" added by
the diff even without the #ifdef.