svn commit: r346553 - stable/11/sys/arm/ti

[Ian Lepore]

Author: ian
Date: Mon Apr 22 14:10:40 2019
New Revision: 346553
URL: https://svnweb.freebsd.org/changeset/base/346553

Log:
  MFC r342652:
  
  Support the SPI mode and bus clock frequency parameters set by the devices
  requesting SPI transfers.
  
  Reported by:	SAITOU Toshihide <toshi at ruby.ocn.ne.jp>

Modified:
  stable/11/sys/arm/ti/ti_spi.c
Directory Properties:
  stable/11/   (props changed)

Modified: stable/11/sys/arm/ti/ti_spi.c
==============================================================================
--- stable/11/sys/arm/ti/ti_spi.c	Mon Apr 22 13:59:21 2019	(r346552)
+++ stable/11/sys/arm/ti/ti_spi.c	Mon Apr 22 14:10:40 2019	(r346553)
@@ -447,7 +447,7 @@ ti_spi_transfer(device_t dev, device_t child, struct s
 {
 	int err;
 	struct ti_spi_softc *sc;
-	uint32_t reg, cs;
+	uint32_t clockhz, cs, mode, reg;
 
 	sc = device_get_softc(dev);
 
@@ -458,6 +458,8 @@ ti_spi_transfer(device_t dev, device_t child, struct s
 
 	/* Get the proper chip select for this child. */
 	spibus_get_cs(child, &cs);
+	spibus_get_clock(child, &clockhz);
+	spibus_get_mode(child, &mode);
 
 	cs &= ~SPIBUS_CS_HIGH;
 
@@ -467,6 +469,13 @@ ti_spi_transfer(device_t dev, device_t child, struct s
 		return (EINVAL);
 	}
 
+	if (mode > 3)
+	{
+	    device_printf(dev, "Invalid mode %d requested by %s\n", mode,
+		    device_get_nameunit(child));
+	    return (EINVAL);
+	}
+
 	TI_SPI_LOCK(sc);
 
 	/* If the controller is in use wait until it is available. */
@@ -488,8 +497,8 @@ ti_spi_transfer(device_t dev, device_t child, struct s
 	/* Disable FIFO for now. */
 	sc->sc_fifolvl = 1;
 
-	/* Use a safe clock - 500kHz. */
-	ti_spi_set_clock(sc, sc->sc_cs, 500000);
+	/* Set the bus frequency. */
+	ti_spi_set_clock(sc, sc->sc_cs, clockhz);
 
 	/* Disable the FIFO. */
 	TI_SPI_WRITE(sc, MCSPI_XFERLEVEL, 0);
@@ -501,6 +510,7 @@ ti_spi_transfer(device_t dev, device_t child, struct s
 	    MCSPI_CONF_DPE1 | MCSPI_CONF_DPE0 | MCSPI_CONF_DMAR |
 	    MCSPI_CONF_DMAW | MCSPI_CONF_EPOL);
 	reg |= MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | MCSPI_CONF_WL8BITS;
+	reg |= mode; /* POL and PHA are the low bits, we can just OR-in mode */
 	TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg);
 
 #if 0