svn commit: r338914 - head/sys/riscv/riscv

[John Baldwin]

Author: jhb
Date: Mon Sep 24 17:41:29 2018
New Revision: 338914
URL: https://svnweb.freebsd.org/changeset/base/338914

Log:
  Implement pmap_sync_icache().
  
  This invokes "fence" on the hart performing the write followed by an IPI
  to execute "fence.i" on all harts.
  
  This is required to support userland debuggers setting breakpoints in
  user processes.
  
  Reviewed by:	br (earlier version), markj
  Approved by:	re (gjb)
  Sponsored by:	DARPA
  Differential Revision:	https://reviews.freebsd.org/D17139

Modified:
  head/sys/riscv/riscv/pmap.c

Modified: head/sys/riscv/riscv/pmap.c
==============================================================================
--- head/sys/riscv/riscv/pmap.c	Mon Sep 24 16:58:55 2018	(r338913)
+++ head/sys/riscv/riscv/pmap.c	Mon Sep 24 17:41:29 2018	(r338914)
@@ -3244,11 +3244,27 @@ pmap_activate(struct thread *td)
 	critical_exit();
 }
 
+static void
+pmap_sync_icache_one(void *arg __unused)
+{
+
+	__asm __volatile("fence.i");
+}
+
 void
 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
 {
 
-	panic("RISCVTODO: pmap_sync_icache");
+	/*
+	 * From the RISC-V User-Level ISA V2.2:
+	 *
+	 * "To make a store to instruction memory visible to all
+	 * RISC-V harts, the writing hart has to execute a data FENCE
+	 * before requesting that all remote RISC-V harts execute a
+	 * FENCE.I."
+	 */
+	__asm __volatile("fence");
+	smp_rendezvous(NULL, pmap_sync_icache_one, NULL, NULL);
 }
 
 /*