svn commit: r339421 - in head/sys: arm/arm arm/conf dts/arm riscv/include riscv/riscv

[Ian Lepore]

On Thu, 2018-10-18 at 15:08 +0000, Ruslan Bukin wrote:
> Author: br
> Date: Thu Oct 18 15:08:14 2018
> New Revision: 339421
> URL: https://svnweb.freebsd.org/changeset/base/339421
> 
> Log:
>   Support RISC-V implementations that do not manage the A and D bits
>   (e.g. RocketChip, lowRISC and derivatives).
>   
>   RISC-V page table entries support A (accessed) and D (dirty) bits. The
>   spec makes hardware support for these bits optional. Implementations that
>   do not manage these bits in hardware raise page faults for accesses to a
>   valid page without A set and writes to a writable page without D set.
>   Check for these types of faults when handling a page fault and fixup the
>   PTE without calling vm_fault if they occur.
>   
>   Reviewed by:	jhb, markj
>   Approved by:	re (gjb)
>   Sponsored by:	DARPA, AFRL
>   Differential Revision:	https://reviews.freebsd.org/D17424
> 
> Modified:
>   head/sys/arm/arm/pl310.c
>   head/sys/arm/conf/GENERIC
>   head/sys/arm/conf/GENERIC-MMCCAM
>   head/sys/arm/conf/SOCDK
>   head/sys/dts/arm/socfpga_arria10_socdk_sdmmc.dts
>   head/sys/riscv/include/pmap.h
>   head/sys/riscv/include/pte.h
>   head/sys/riscv/riscv/locore.S
>   head/sys/riscv/riscv/pmap.c
>   head/sys/riscv/riscv/trap.c
> 

It looks like some unintended arm files got included in this commit.

-- Ian