svn commit: r341296 - head/sys/dev/sfxge/common

[Andrew Rybchenko]

Author: arybchik
Date: Fri Nov 30 07:05:23 2018
New Revision: 341296
URL: https://svnweb.freebsd.org/changeset/base/341296

Log:
  sfxge(4): add information if TSO workaround is required
  
  In SF bug 61297 it's been confirmed that the hardware does not always
  calculate the TCP checksum correctly with TSO sends.
  
  The value of the Total Length field (IPv4) or Payload Length field
  (IPv6) is the critical factor. We're sufficiently confident that if
  these fields are zero then the checksum will be calculated correctly.
  
  The information may be used by the drivers to check if the workaround is
  required when FATSOv2 is implemented.
  
  Submitted by:   Mark Spender <mspender at solarflare.com>
  Sponsored by:   Solarflare Communications, Inc.
  Differential Revision:  https://reviews.freebsd.org/D18258

Modified:
  head/sys/dev/sfxge/common/efx.h
  head/sys/dev/sfxge/common/hunt_nic.c
  head/sys/dev/sfxge/common/medford2_nic.c
  head/sys/dev/sfxge/common/medford_nic.c

Modified: head/sys/dev/sfxge/common/efx.h
==============================================================================
--- head/sys/dev/sfxge/common/efx.h	Fri Nov 30 07:05:12 2018	(r341295)
+++ head/sys/dev/sfxge/common/efx.h	Fri Nov 30 07:05:23 2018	(r341296)
@@ -1320,6 +1320,7 @@ typedef struct efx_nic_cfg_s {
 	boolean_t		enc_bug35388_workaround;
 	boolean_t		enc_bug41750_workaround;
 	boolean_t		enc_bug61265_workaround;
+	boolean_t		enc_bug61297_workaround;
 	boolean_t		enc_rx_batching_enabled;
 	/* Maximum number of descriptors completed in an rx event. */
 	uint32_t		enc_rx_batch_max;

Modified: head/sys/dev/sfxge/common/hunt_nic.c
==============================================================================
--- head/sys/dev/sfxge/common/hunt_nic.c	Fri Nov 30 07:05:12 2018	(r341295)
+++ head/sys/dev/sfxge/common/hunt_nic.c	Fri Nov 30 07:05:23 2018	(r341296)
@@ -217,6 +217,9 @@ hunt_board_cfg(
 
 	encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
 
+	/* Checksums for TSO sends can be incorrect on Huntington. */
+	encp->enc_bug61297_workaround = B_TRUE;
+
 	/* Alignment for receive packet DMA buffers */
 	encp->enc_rx_buf_align_start = 1;
 	encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */

Modified: head/sys/dev/sfxge/common/medford2_nic.c
==============================================================================
--- head/sys/dev/sfxge/common/medford2_nic.c	Fri Nov 30 07:05:12 2018	(r341295)
+++ head/sys/dev/sfxge/common/medford2_nic.c	Fri Nov 30 07:05:23 2018	(r341296)
@@ -125,6 +125,9 @@ medford2_board_cfg(
 	else
 		goto fail1;
 
+	/* Checksums for TSO sends should always be correct on Medford2. */
+	encp->enc_bug61297_workaround = B_FALSE;
+
 	/* Get clock frequencies (in MHz). */
 	if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
 		goto fail2;

Modified: head/sys/dev/sfxge/common/medford_nic.c
==============================================================================
--- head/sys/dev/sfxge/common/medford_nic.c	Fri Nov 30 07:05:12 2018	(r341295)
+++ head/sys/dev/sfxge/common/medford_nic.c	Fri Nov 30 07:05:23 2018	(r341296)
@@ -121,6 +121,9 @@ medford_board_cfg(
 	else
 		goto fail1;
 
+	/* Checksums for TSO sends can be incorrect on Medford. */
+	encp->enc_bug61297_workaround = B_TRUE;
+
 	/* Get clock frequencies (in MHz). */
 	if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
 		goto fail2;