svn commit: r334433 - head/sys/arm/allwinner

[Emmanuel Vadot]

Author: manu
Date: Thu May 31 15:36:26 2018
New Revision: 334433
URL: https://svnweb.freebsd.org/changeset/base/334433

Log:
  aw_mmc: Rename clock register defines consistently

Modified:
  head/sys/arm/allwinner/aw_mmc.c
  head/sys/arm/allwinner/aw_mmc.h

Modified: head/sys/arm/allwinner/aw_mmc.c
==============================================================================
--- head/sys/arm/allwinner/aw_mmc.c	Thu May 31 14:38:13 2018	(r334432)
+++ head/sys/arm/allwinner/aw_mmc.c	Thu May 31 15:36:26 2018	(r334433)
@@ -885,13 +885,13 @@ aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t 
 	int retry;
 
 	reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
-	reg &= ~(AW_MMC_CKCR_CCLK_ENB | AW_MMC_CKCR_CCLK_CTRL |
-	    AW_MMC_CKCR_CCLK_MASK_DATA0);
+	reg &= ~(AW_MMC_CKCR_ENB | AW_MMC_CKCR_LOW_POWER |
+	    AW_MMC_CKCR_MASK_DATA0);
 
 	if (clkon)
-		reg |= AW_MMC_CKCR_CCLK_ENB;
+		reg |= AW_MMC_CKCR_ENB;
 	if (sc->aw_mmc_conf->mask_data0)
-		reg |= AW_MMC_CKCR_CCLK_MASK_DATA0;
+		reg |= AW_MMC_CKCR_MASK_DATA0;
 
 	AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
 
@@ -913,7 +913,7 @@ aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t 
 
 	if (sc->aw_mmc_conf->mask_data0) {
 		reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
-		reg &= ~AW_MMC_CKCR_CCLK_MASK_DATA0;
+		reg &= ~AW_MMC_CKCR_MASK_DATA0;
 		AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
 	}
 
@@ -1030,7 +1030,7 @@ aw_mmc_update_ios(device_t bus, device_t child)
 
 		/* Reset the divider. */
 		reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
-		reg &= ~AW_MMC_CKCR_CCLK_DIV;
+		reg &= ~AW_MMC_CKCR_DIV;
 		reg |= div - 1;
 		AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
 

Modified: head/sys/arm/allwinner/aw_mmc.h
==============================================================================
--- head/sys/arm/allwinner/aw_mmc.h	Thu May 31 14:38:13 2018	(r334432)
+++ head/sys/arm/allwinner/aw_mmc.h	Thu May 31 15:36:26 2018	(r334433)
@@ -82,10 +82,10 @@
 	(AW_MMC_GCTL_SOFT_RST | AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST)
 
 /* AW_MMC_CKCR */
-#define	AW_MMC_CKCR_CCLK_ENB		(1U << 16)
-#define	AW_MMC_CKCR_CCLK_CTRL		(1U << 17)
-#define	AW_MMC_CKCR_CCLK_MASK_DATA0	(1U << 31)
-#define	AW_MMC_CKCR_CCLK_DIV		0xff
+#define	AW_MMC_CKCR_DIV		0xff
+#define	AW_MMC_CKCR_ENB		(1U << 16)
+#define	AW_MMC_CKCR_LOW_POWER	(1U << 17)
+#define	AW_MMC_CKCR_MASK_DATA0	(1U << 31)
 
 /* AW_MMC_TMOR */
 #define	AW_MMC_TMOR_RTO_LMT_SHIFT(x)	x		/* Response timeout limit */