svn commit: r334006 - head/sys/arm/allwinner

[Emmanuel Vadot]

Author: manu
Date: Mon May 21 21:15:46 2018
New Revision: 334006
URL: https://svnweb.freebsd.org/changeset/base/334006

Log:
  aw_mmc: Correctly reset the mmc controller
  
  Always disable FIFO access as we don't use it.
  Rename some register bits so they are in sync with the register name.
  
  While here add my copyright as I've probably wrote 70% of the code here.

Modified:
  head/sys/arm/allwinner/aw_mmc.c
  head/sys/arm/allwinner/aw_mmc.h

Modified: head/sys/arm/allwinner/aw_mmc.c
==============================================================================
--- head/sys/arm/allwinner/aw_mmc.c	Mon May 21 21:08:19 2018	(r334005)
+++ head/sys/arm/allwinner/aw_mmc.c	Mon May 21 21:15:46 2018	(r334006)
@@ -1,4 +1,7 @@
 /*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2018 Emmanuel Vadot <manu at FreeBSD.org>
  * Copyright (c) 2013 Alexander Fedorov
  * All rights reserved.
  *
@@ -431,12 +434,12 @@ aw_mmc_prepare_dma(struct aw_mmc_softc *sc)
 
 	/* Enable DMA */
 	val = AW_MMC_READ_4(sc, AW_MMC_GCTL);
-	val &= ~AW_MMC_CTRL_FIFO_AC_MOD;
-	val |= AW_MMC_CTRL_DMA_ENB;
+	val &= ~AW_MMC_GCTL_FIFO_AC_MOD;
+	val |= AW_MMC_GCTL_DMA_ENB;
 	AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val);
 
 	/* Reset DMA */
-	val |= AW_MMC_CTRL_DMA_RST;
+	val |= AW_MMC_GCTL_DMA_RST;
 	AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val);
 
 	AW_MMC_WRITE_4(sc, AW_MMC_DMAC, AW_MMC_DMAC_IDMAC_SOFT_RST);
@@ -463,12 +466,15 @@ aw_mmc_prepare_dma(struct aw_mmc_softc *sc)
 static int
 aw_mmc_reset(struct aw_mmc_softc *sc)
 {
+	uint32_t reg;
 	int timeout;
 
-	AW_MMC_WRITE_4(sc, AW_MMC_GCTL, AW_MMC_RESET);
+	reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);
+	reg |= AW_MMC_GCTL_RESET;
+	AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);
 	timeout = 1000;
 	while (--timeout > 0) {
-		if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & AW_MMC_RESET) == 0)
+		if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & AW_MMC_GCTL_RESET) == 0)
 			break;
 		DELAY(100);
 	}
@@ -481,6 +487,7 @@ aw_mmc_reset(struct aw_mmc_softc *sc)
 static int
 aw_mmc_init(struct aw_mmc_softc *sc)
 {
+	uint32_t reg;
 	int ret;
 
 	ret = aw_mmc_reset(sc);
@@ -506,9 +513,12 @@ aw_mmc_init(struct aw_mmc_softc *sc)
 
 	AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff);
 
-	/* Enable interrupts and AHB access. */
-	AW_MMC_WRITE_4(sc, AW_MMC_GCTL,
-	    AW_MMC_READ_4(sc, AW_MMC_GCTL) | AW_MMC_CTRL_INT_ENB);
+	/* Enable interrupts and disable AHB access. */
+	reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);
+	reg |= AW_MMC_GCTL_INT_ENB;
+	reg &= ~AW_MMC_GCTL_FIFO_AC_MOD;
+	reg &= ~AW_MMC_GCTL_WAIT_MEM_ACCESS;
+	AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);
 
 	return (0);
 }
@@ -524,7 +534,7 @@ aw_mmc_req_done(struct aw_mmc_softc *sc)
 	cmd = sc->aw_req->cmd;
 	if (cmd->error != MMC_ERR_NONE) {
 		/* Reset the FIFO and DMA engines. */
-		mask = AW_MMC_CTRL_FIFO_RST | AW_MMC_CTRL_DMA_RST;
+		mask = AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST;
 		val = AW_MMC_READ_4(sc, AW_MMC_GCTL);
 		AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val | mask);
 
@@ -998,9 +1008,9 @@ aw_mmc_update_ios(device_t bus, device_t child)
 	reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);
 	if (ios->timing == bus_timing_uhs_ddr50 ||
 	  ios->timing == bus_timing_mmc_ddr52)
-		reg |= AW_MMC_CTRL_DDR_MOD_SEL;
+		reg |= AW_MMC_GCTL_DDR_MOD_SEL;
 	else
-		reg &= ~AW_MMC_CTRL_DDR_MOD_SEL;
+		reg &= ~AW_MMC_GCTL_DDR_MOD_SEL;
 	AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);
 
 	if (ios->clock && ios->clock != sc->aw_clock) {

Modified: head/sys/arm/allwinner/aw_mmc.h
==============================================================================
--- head/sys/arm/allwinner/aw_mmc.h	Mon May 21 21:08:19 2018	(r334005)
+++ head/sys/arm/allwinner/aw_mmc.h	Mon May 21 21:15:46 2018	(r334006)
@@ -1,4 +1,7 @@
 /*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2018 Emmanuel Vadot <manu at FreeBSD.org>
  * Copyright (c) 2013 Alexander Fedorov <alexander.fedorov at rtlservice.com>
  * All rights reserved.
  *
@@ -66,16 +69,17 @@
 #define	A31_MMC_FIFO		0x200	/* FIFO Access Address (A31) */
 
 /* AW_MMC_GCTL */
-#define	AW_MMC_CTRL_SOFT_RST		(1U << 0)
-#define	AW_MMC_CTRL_FIFO_RST		(1U << 1)
-#define	AW_MMC_CTRL_DMA_RST		(1U << 2)
-#define	AW_MMC_CTRL_INT_ENB		(1U << 4)
-#define	AW_MMC_CTRL_DMA_ENB		(1U << 5)
-#define	AW_MMC_CTRL_CD_DBC_ENB		(1U << 8)
-#define	AW_MMC_CTRL_DDR_MOD_SEL		(1U << 10)
-#define	AW_MMC_CTRL_FIFO_AC_MOD		(1U << 31)
-#define	AW_MMC_RESET					\
-	(AW_MMC_CTRL_SOFT_RST | AW_MMC_CTRL_FIFO_RST | AW_MMC_CTRL_DMA_RST)
+#define	AW_MMC_GCTL_SOFT_RST		(1U << 0)
+#define	AW_MMC_GCTL_FIFO_RST		(1U << 1)
+#define	AW_MMC_GCTL_DMA_RST		(1U << 2)
+#define	AW_MMC_GCTL_INT_ENB		(1U << 4)
+#define	AW_MMC_GCTL_DMA_ENB		(1U << 5)
+#define	AW_MMC_GCTL_CD_DBC_ENB		(1U << 8)
+#define	AW_MMC_GCTL_DDR_MOD_SEL		(1U << 10)
+#define	AW_MMC_GCTL_WAIT_MEM_ACCESS	(1U << 30)
+#define	AW_MMC_GCTL_FIFO_AC_MOD		(1U << 31)
+#define	AW_MMC_GCTL_RESET			\
+	(AW_MMC_GCTL_SOFT_RST | AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST)
 
 /* AW_MMC_CKCR */
 #define	AW_MMC_CKCR_CCLK_ENB		(1U << 16)