svn commit: r331219 - in stable/11: contrib/llvm/include/llvm contrib/llvm/include/llvm/CodeGen contrib/llvm/include/llvm/Target contrib/llvm/lib/CodeGen contrib/llvm/lib/Target/X86 contrib/llvm/to...
Dimitry Andric
dim at FreeBSD.org
Mon Mar 19 18:36:47 UTC 2018
Author: dim
Date: Mon Mar 19 18:36:43 2018
New Revision: 331219
URL: https://svnweb.freebsd.org/changeset/base/331219
Log:
Merge retpoline support from the upstream llvm, clang and lld 5.0
branches. Upstream merge revisions:
r324007: merging r323155 for llvm
r324009: merging r323915 for llvm
r324012: merging r323155 for clang
r324025: merging r323155 for lld, with modifications to
handle int3 fill
r324026: merging r323288 for lld
r325088: merging r324449 for llvm
r325089: merging r324645 for llvm
r325090: merging r325049 for llvm
r325091: merging r325085 for llvm
Original commit messages:
r323155 (by Chandler Carruth):
Introduce the "retpoline" x86 mitigation technique for variant #2 of
the speculative execution vulnerabilities disclosed today,
specifically identified by CVE-2017-5715, "Branch Target Injection",
and is one of the two halves to Spectre.
Summary:
First, we need to explain the core of the vulnerability. Note that
this is a very incomplete description, please see the Project Zero
blog post for details:
https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html
The basis for branch target injection is to direct speculative
execution of the processor to some "gadget" of executable code by
poisoning the prediction of indirect branches with the address of
that gadget. The gadget in turn contains an operation that provides a
side channel for reading data. Most commonly, this will look like a
load of secret data followed by a branch on the loaded value and then
a load of some predictable cache line. The attacker then uses timing
of the processors cache to determine which direction the branch took
*in the speculative execution*, and in turn what one bit of the
loaded value was. Due to the nature of these timing side channels and
the branch predictor on Intel processors, this allows an attacker to
leak data only accessible to a privileged domain (like the kernel)
back into an unprivileged domain.
The goal is simple: avoid generating code which contains an indirect
branch that could have its prediction poisoned by an attacker. In
many cases, the compiler can simply use directed conditional branches
and a small search tree. LLVM already has support for lowering
switches in this way and the first step of this patch is to disable
jump-table lowering of switches and introduce a pass to rewrite
explicit indirectbr sequences into a switch over integers.
However, there is no fully general alternative to indirect calls. We
introduce a new construct we call a "retpoline" to implement indirect
calls in a non-speculatable way. It can be thought of loosely as a
trampoline for indirect calls which uses the RET instruction on x86.
Further, we arrange for a specific call->ret sequence which ensures
the processor predicts the return to go to a controlled, known
location. The retpoline then "smashes" the return address pushed onto
the stack by the call with the desired target of the original
indirect call. The result is a predicted return to the next
instruction after a call (which can be used to trap speculative
execution within an infinite loop) and an actual indirect branch to
an arbitrary address.
On 64-bit x86 ABIs, this is especially easily done in the compiler by
using a guaranteed scratch register to pass the target into this
device. For 32-bit ABIs there isn't a guaranteed scratch register
and so several different retpoline variants are introduced to use a
scratch register if one is available in the calling convention and to
otherwise use direct stack push/pop sequences to pass the target
address.
This "retpoline" mitigation is fully described in the following blog
post: https://support.google.com/faqs/answer/7625886
We also support a target feature that disables emission of the
retpoline thunk by the compiler to allow for custom thunks if users
want them. These are particularly useful in environments like
kernels that routinely do hot-patching on boot and want to hot-patch
their thunk to different code sequences. They can write this custom
thunk and use `-mretpoline-external-thunk` *in addition* to
`-mretpoline`. In this case, on x86-64 thu thunk names must be:
```
__llvm_external_retpoline_r11
```
or on 32-bit:
```
__llvm_external_retpoline_eax
__llvm_external_retpoline_ecx
__llvm_external_retpoline_edx
__llvm_external_retpoline_push
```
And the target of the retpoline is passed in the named register, or
in the case of the `push` suffix on the top of the stack via a
`pushl` instruction.
There is one other important source of indirect branches in x86 ELF
binaries: the PLT. These patches also include support for LLD to
generate PLT entries that perform a retpoline-style indirection.
The only other indirect branches remaining that we are aware of are
from precompiled runtimes (such as crt0.o and similar). The ones we
have found are not really attackable, and so we have not focused on
them here, but eventually these runtimes should also be replicated
for retpoline-ed configurations for completeness.
For kernels or other freestanding or fully static executables, the
compiler switch `-mretpoline` is sufficient to fully mitigate this
particular attack. For dynamic executables, you must compile *all*
libraries with `-mretpoline` and additionally link the dynamic
executable and all shared libraries with LLD and pass `-z
retpolineplt` (or use similar functionality from some other linker).
We strongly recommend also using `-z now` as non-lazy binding allows
the retpoline-mitigated PLT to be substantially smaller.
When manually apply similar transformations to `-mretpoline` to the
Linux kernel we observed very small performance hits to applications
running typical workloads, and relatively minor hits (approximately
2%) even for extremely syscall-heavy applications. This is largely
due to the small number of indirect branches that occur in
performance sensitive paths of the kernel.
When using these patches on statically linked applications,
especially C++ applications, you should expect to see a much more
dramatic performance hit. For microbenchmarks that are switch,
indirect-, or virtual-call heavy we have seen overheads ranging from
10% to 50%.
However, real-world workloads exhibit substantially lower performance
impact. Notably, techniques such as PGO and ThinLTO dramatically
reduce the impact of hot indirect calls (by speculatively promoting
them to direct calls) and allow optimized search trees to be used to
lower switches. If you need to deploy these techniques in C++
applications, we *strongly* recommend that you ensure all hot call
targets are statically linked (avoiding PLT indirection) and use both
PGO and ThinLTO. Well tuned servers using all of these techniques saw
5% - 10% overhead from the use of retpoline.
We will add detailed documentation covering these components in
subsequent patches, but wanted to make the core functionality
available as soon as possible. Happy for more code review, but we'd
really like to get these patches landed and backported ASAP for
obvious reasons. We're planning to backport this to both 6.0 and 5.0
release streams and get a 5.0 release with just this cherry picked
ASAP for distros and vendors.
This patch is the work of a number of people over the past month:
Eric, Reid, Rui, and myself. I'm mailing it out as a single commit
due to the time sensitive nature of landing this and the need to
backport it. Huge thanks to everyone who helped out here, and
everyone at Intel who helped out in discussions about how to craft
this. Also, credit goes to Paul Turner (at Google, but not an LLVM
contributor) for much of the underlying retpoline design.
Reviewers: echristo, rnk, ruiu, craig.topper, DavidKreitzer
Subscribers: sanjoy, emaste, mcrosier, mgorny, mehdi_amini,
hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D41723
r323915 (by Chandler Carruth):
[x86] Make the retpoline thunk insertion a machine function pass.
Summary:
This removes the need for a machine module pass using some deeply
questionable hacks. This should address PR36123 which is a case where
in full LTO the memory usage of a machine module pass actually ended
up being significant.
We should revert this on trunk as soon as we understand and fix the
memory usage issue, but we should include this in any backports of
retpolines themselves.
Reviewers: echristo, MatzeB
Subscribers: sanjoy, mcrosier, mehdi_amini, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D42726
r323288 (by Rui Ueyama):
Fix retpoline PLT header size for i386.
Differential Revision: https://reviews.llvm.org/D42397
r324449 (by Chandler Carruth):
[x86/retpoline] Make the external thunk names exactly match the names
that happened to end up in GCC.
This is really unfortunate, as the names don't have much rhyme or
reason to them. Originally in the discussions it seemed fine to rely
on aliases to map different names to whatever external thunk code
developers wished to use but there are practical problems with that
in the kernel it turns out. And since we're discovering this
practical problems late and since GCC has already shipped a release
with one set of names, we are forced, yet again, to blindly match
what is there.
Somewhat rushing this patch out for the Linux kernel folks to test
and so we can get it patched into our releases.
Differential Revision: https://reviews.llvm.org/D42998
r324645 (by David Woodhouse):
[X86] Support 'V' register operand modifier
This allows the register name to be printed without the leading '%'.
This can be used for emitting calls to the retpoline thunks from
inline asm.
r325049 (by Reid Kleckner):
[X86] Use EDI for retpoline when no scratch regs are left
Summary:
Instead of solving the hard problem of how to pass the callee to the
indirect jump thunk without a register, just use a CSR. At a call
boundary, there's nothing stopping us from using a CSR to hold the
callee as long as we save and restore it in the prologue.
Also, add tests for this mregparm=3 case. I wrote execution tests for
__llvm_retpoline_push, but they never got committed as lit tests,
either because I never rewrote them or because they got lost in merge
conflicts.
Reviewers: chandlerc, dwmw2
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D43214
r325085 (by Reid Kleckner):
[X86] Remove dead code from retpoline thunk generation
Differential Revision: https://reviews.freebsd.org/D14720
Added:
stable/11/contrib/llvm/lib/CodeGen/IndirectBrExpandPass.cpp
stable/11/contrib/llvm/lib/Target/X86/X86RetpolineThunks.cpp
Modified:
stable/11/contrib/llvm/include/llvm/CodeGen/Passes.h
stable/11/contrib/llvm/include/llvm/CodeGen/TargetPassConfig.h
stable/11/contrib/llvm/include/llvm/InitializePasses.h
stable/11/contrib/llvm/include/llvm/Target/TargetLowering.h
stable/11/contrib/llvm/include/llvm/Target/TargetSubtargetInfo.h
stable/11/contrib/llvm/lib/CodeGen/CodeGen.cpp
stable/11/contrib/llvm/lib/CodeGen/TargetPassConfig.cpp
stable/11/contrib/llvm/lib/CodeGen/TargetSubtargetInfo.cpp
stable/11/contrib/llvm/lib/Target/X86/X86.h
stable/11/contrib/llvm/lib/Target/X86/X86.td
stable/11/contrib/llvm/lib/Target/X86/X86AsmPrinter.cpp
stable/11/contrib/llvm/lib/Target/X86/X86AsmPrinter.h
stable/11/contrib/llvm/lib/Target/X86/X86FastISel.cpp
stable/11/contrib/llvm/lib/Target/X86/X86FrameLowering.cpp
stable/11/contrib/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
stable/11/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp
stable/11/contrib/llvm/lib/Target/X86/X86ISelLowering.h
stable/11/contrib/llvm/lib/Target/X86/X86InstrCompiler.td
stable/11/contrib/llvm/lib/Target/X86/X86InstrControl.td
stable/11/contrib/llvm/lib/Target/X86/X86InstrInfo.td
stable/11/contrib/llvm/lib/Target/X86/X86MCInstLower.cpp
stable/11/contrib/llvm/lib/Target/X86/X86Subtarget.cpp
stable/11/contrib/llvm/lib/Target/X86/X86Subtarget.h
stable/11/contrib/llvm/lib/Target/X86/X86TargetMachine.cpp
stable/11/contrib/llvm/tools/clang/include/clang/Driver/Options.td
stable/11/contrib/llvm/tools/clang/lib/Basic/Targets.cpp
stable/11/contrib/llvm/tools/lld/ELF/Arch/X86.cpp
stable/11/contrib/llvm/tools/lld/ELF/Arch/X86_64.cpp
stable/11/contrib/llvm/tools/lld/ELF/Config.h
stable/11/contrib/llvm/tools/lld/ELF/Driver.cpp
stable/11/contrib/llvm/tools/opt/opt.cpp
stable/11/lib/clang/freebsd_cc_version.h
stable/11/lib/clang/libllvm/Makefile
stable/11/sys/sys/param.h
Modified: stable/11/contrib/llvm/include/llvm/CodeGen/Passes.h
==============================================================================
--- stable/11/contrib/llvm/include/llvm/CodeGen/Passes.h Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/include/llvm/CodeGen/Passes.h Mon Mar 19 18:36:43 2018 (r331219)
@@ -420,6 +420,9 @@ namespace llvm {
/// shuffles.
FunctionPass *createExpandReductionsPass();
+ // This pass expands indirectbr instructions.
+ FunctionPass *createIndirectBrExpandPass();
+
} // End llvm namespace
#endif
Modified: stable/11/contrib/llvm/include/llvm/CodeGen/TargetPassConfig.h
==============================================================================
--- stable/11/contrib/llvm/include/llvm/CodeGen/TargetPassConfig.h Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/include/llvm/CodeGen/TargetPassConfig.h Mon Mar 19 18:36:43 2018 (r331219)
@@ -406,6 +406,13 @@ class TargetPassConfig : public ImmutablePass { (prote
/// immediately before machine code is emitted.
virtual void addPreEmitPass() { }
+ /// Targets may add passes immediately before machine code is emitted in this
+ /// callback. This is called even later than `addPreEmitPass`.
+ // FIXME: Rename `addPreEmitPass` to something more sensible given its actual
+ // position and remove the `2` suffix here as this callback is what
+ // `addPreEmitPass` *should* be but in reality isn't.
+ virtual void addPreEmitPass2() {}
+
/// Utilities for targets to add passes to the pass manager.
///
Modified: stable/11/contrib/llvm/include/llvm/InitializePasses.h
==============================================================================
--- stable/11/contrib/llvm/include/llvm/InitializePasses.h Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/include/llvm/InitializePasses.h Mon Mar 19 18:36:43 2018 (r331219)
@@ -157,6 +157,7 @@ void initializeIVUsersWrapperPassPass(PassRegistry&);
void initializeIfConverterPass(PassRegistry&);
void initializeImplicitNullChecksPass(PassRegistry&);
void initializeIndVarSimplifyLegacyPassPass(PassRegistry&);
+void initializeIndirectBrExpandPassPass(PassRegistry&);
void initializeInductiveRangeCheckEliminationPass(PassRegistry&);
void initializeInferAddressSpacesPass(PassRegistry&);
void initializeInferFunctionAttrsLegacyPassPass(PassRegistry&);
Modified: stable/11/contrib/llvm/include/llvm/Target/TargetLowering.h
==============================================================================
--- stable/11/contrib/llvm/include/llvm/Target/TargetLowering.h Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/include/llvm/Target/TargetLowering.h Mon Mar 19 18:36:43 2018 (r331219)
@@ -799,7 +799,7 @@ class TargetLoweringBase { (public)
}
/// Return true if lowering to a jump table is allowed.
- bool areJTsAllowed(const Function *Fn) const {
+ virtual bool areJTsAllowed(const Function *Fn) const {
if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
return false;
Modified: stable/11/contrib/llvm/include/llvm/Target/TargetSubtargetInfo.h
==============================================================================
--- stable/11/contrib/llvm/include/llvm/Target/TargetSubtargetInfo.h Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/include/llvm/Target/TargetSubtargetInfo.h Mon Mar 19 18:36:43 2018 (r331219)
@@ -172,6 +172,9 @@ class TargetSubtargetInfo : public MCSubtargetInfo { (
/// \brief True if the subtarget should run the atomic expansion pass.
virtual bool enableAtomicExpand() const;
+ /// True if the subtarget should run the indirectbr expansion pass.
+ virtual bool enableIndirectBrExpand() const;
+
/// \brief Override generic scheduling policy within a region.
///
/// This is a convenient way for targets that don't provide any custom
Modified: stable/11/contrib/llvm/lib/CodeGen/CodeGen.cpp
==============================================================================
--- stable/11/contrib/llvm/lib/CodeGen/CodeGen.cpp Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/lib/CodeGen/CodeGen.cpp Mon Mar 19 18:36:43 2018 (r331219)
@@ -39,6 +39,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeGCModuleInfoPass(Registry);
initializeIfConverterPass(Registry);
initializeImplicitNullChecksPass(Registry);
+ initializeIndirectBrExpandPassPass(Registry);
initializeInterleavedAccessPass(Registry);
initializeLiveDebugValuesPass(Registry);
initializeLiveDebugVariablesPass(Registry);
Added: stable/11/contrib/llvm/lib/CodeGen/IndirectBrExpandPass.cpp
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ stable/11/contrib/llvm/lib/CodeGen/IndirectBrExpandPass.cpp Mon Mar 19 18:36:43 2018 (r331219)
@@ -0,0 +1,221 @@
+//===- IndirectBrExpandPass.cpp - Expand indirectbr to switch -------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+/// \file
+///
+/// Implements an expansion pass to turn `indirectbr` instructions in the IR
+/// into `switch` instructions. This works by enumerating the basic blocks in
+/// a dense range of integers, replacing each `blockaddr` constant with the
+/// corresponding integer constant, and then building a switch that maps from
+/// the integers to the actual blocks. All of the indirectbr instructions in the
+/// function are redirected to this common switch.
+///
+/// While this is generically useful if a target is unable to codegen
+/// `indirectbr` natively, it is primarily useful when there is some desire to
+/// get the builtin non-jump-table lowering of a switch even when the input
+/// source contained an explicit indirect branch construct.
+///
+/// Note that it doesn't make any sense to enable this pass unless a target also
+/// disables jump-table lowering of switches. Doing that is likely to pessimize
+/// the code.
+///
+//===----------------------------------------------------------------------===//
+
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/Sequence.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
+#include "llvm/IR/BasicBlock.h"
+#include "llvm/IR/Function.h"
+#include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/InstIterator.h"
+#include "llvm/IR/Instruction.h"
+#include "llvm/IR/Instructions.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetMachine.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "indirectbr-expand"
+
+namespace {
+
+class IndirectBrExpandPass : public FunctionPass {
+ const TargetLowering *TLI = nullptr;
+
+public:
+ static char ID; // Pass identification, replacement for typeid
+
+ IndirectBrExpandPass() : FunctionPass(ID) {
+ initializeIndirectBrExpandPassPass(*PassRegistry::getPassRegistry());
+ }
+
+ bool runOnFunction(Function &F) override;
+};
+
+} // end anonymous namespace
+
+char IndirectBrExpandPass::ID = 0;
+
+INITIALIZE_PASS(IndirectBrExpandPass, DEBUG_TYPE,
+ "Expand indirectbr instructions", false, false)
+
+FunctionPass *llvm::createIndirectBrExpandPass() {
+ return new IndirectBrExpandPass();
+}
+
+bool IndirectBrExpandPass::runOnFunction(Function &F) {
+ auto &DL = F.getParent()->getDataLayout();
+ auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
+ if (!TPC)
+ return false;
+
+ auto &TM = TPC->getTM<TargetMachine>();
+ auto &STI = *TM.getSubtargetImpl(F);
+ if (!STI.enableIndirectBrExpand())
+ return false;
+ TLI = STI.getTargetLowering();
+
+ SmallVector<IndirectBrInst *, 1> IndirectBrs;
+
+ // Set of all potential successors for indirectbr instructions.
+ SmallPtrSet<BasicBlock *, 4> IndirectBrSuccs;
+
+ // Build a list of indirectbrs that we want to rewrite.
+ for (BasicBlock &BB : F)
+ if (auto *IBr = dyn_cast<IndirectBrInst>(BB.getTerminator())) {
+ // Handle the degenerate case of no successors by replacing the indirectbr
+ // with unreachable as there is no successor available.
+ if (IBr->getNumSuccessors() == 0) {
+ (void)new UnreachableInst(F.getContext(), IBr);
+ IBr->eraseFromParent();
+ continue;
+ }
+
+ IndirectBrs.push_back(IBr);
+ for (BasicBlock *SuccBB : IBr->successors())
+ IndirectBrSuccs.insert(SuccBB);
+ }
+
+ if (IndirectBrs.empty())
+ return false;
+
+ // If we need to replace any indirectbrs we need to establish integer
+ // constants that will correspond to each of the basic blocks in the function
+ // whose address escapes. We do that here and rewrite all the blockaddress
+ // constants to just be those integer constants cast to a pointer type.
+ SmallVector<BasicBlock *, 4> BBs;
+
+ for (BasicBlock &BB : F) {
+ // Skip blocks that aren't successors to an indirectbr we're going to
+ // rewrite.
+ if (!IndirectBrSuccs.count(&BB))
+ continue;
+
+ auto IsBlockAddressUse = [&](const Use &U) {
+ return isa<BlockAddress>(U.getUser());
+ };
+ auto BlockAddressUseIt = llvm::find_if(BB.uses(), IsBlockAddressUse);
+ if (BlockAddressUseIt == BB.use_end())
+ continue;
+
+ assert(std::find_if(std::next(BlockAddressUseIt), BB.use_end(),
+ IsBlockAddressUse) == BB.use_end() &&
+ "There should only ever be a single blockaddress use because it is "
+ "a constant and should be uniqued.");
+
+ auto *BA = cast<BlockAddress>(BlockAddressUseIt->getUser());
+
+ // Skip if the constant was formed but ended up not being used (due to DCE
+ // or whatever).
+ if (!BA->isConstantUsed())
+ continue;
+
+ // Compute the index we want to use for this basic block. We can't use zero
+ // because null can be compared with block addresses.
+ int BBIndex = BBs.size() + 1;
+ BBs.push_back(&BB);
+
+ auto *ITy = cast<IntegerType>(DL.getIntPtrType(BA->getType()));
+ ConstantInt *BBIndexC = ConstantInt::get(ITy, BBIndex);
+
+ // Now rewrite the blockaddress to an integer constant based on the index.
+ // FIXME: We could potentially preserve the uses as arguments to inline asm.
+ // This would allow some uses such as diagnostic information in crashes to
+ // have higher quality even when this transform is enabled, but would break
+ // users that round-trip blockaddresses through inline assembly and then
+ // back into an indirectbr.
+ BA->replaceAllUsesWith(ConstantExpr::getIntToPtr(BBIndexC, BA->getType()));
+ }
+
+ if (BBs.empty()) {
+ // There are no blocks whose address is taken, so any indirectbr instruction
+ // cannot get a valid input and we can replace all of them with unreachable.
+ for (auto *IBr : IndirectBrs) {
+ (void)new UnreachableInst(F.getContext(), IBr);
+ IBr->eraseFromParent();
+ }
+ return true;
+ }
+
+ BasicBlock *SwitchBB;
+ Value *SwitchValue;
+
+ // Compute a common integer type across all the indirectbr instructions.
+ IntegerType *CommonITy = nullptr;
+ for (auto *IBr : IndirectBrs) {
+ auto *ITy =
+ cast<IntegerType>(DL.getIntPtrType(IBr->getAddress()->getType()));
+ if (!CommonITy || ITy->getBitWidth() > CommonITy->getBitWidth())
+ CommonITy = ITy;
+ }
+
+ auto GetSwitchValue = [DL, CommonITy](IndirectBrInst *IBr) {
+ return CastInst::CreatePointerCast(
+ IBr->getAddress(), CommonITy,
+ Twine(IBr->getAddress()->getName()) + ".switch_cast", IBr);
+ };
+
+ if (IndirectBrs.size() == 1) {
+ // If we only have one indirectbr, we can just directly replace it within
+ // its block.
+ SwitchBB = IndirectBrs[0]->getParent();
+ SwitchValue = GetSwitchValue(IndirectBrs[0]);
+ IndirectBrs[0]->eraseFromParent();
+ } else {
+ // Otherwise we need to create a new block to hold the switch across BBs,
+ // jump to that block instead of each indirectbr, and phi together the
+ // values for the switch.
+ SwitchBB = BasicBlock::Create(F.getContext(), "switch_bb", &F);
+ auto *SwitchPN = PHINode::Create(CommonITy, IndirectBrs.size(),
+ "switch_value_phi", SwitchBB);
+ SwitchValue = SwitchPN;
+
+ // Now replace the indirectbr instructions with direct branches to the
+ // switch block and fill out the PHI operands.
+ for (auto *IBr : IndirectBrs) {
+ SwitchPN->addIncoming(GetSwitchValue(IBr), IBr->getParent());
+ BranchInst::Create(SwitchBB, IBr);
+ IBr->eraseFromParent();
+ }
+ }
+
+ // Now build the switch in the block. The block will have no terminator
+ // already.
+ auto *SI = SwitchInst::Create(SwitchValue, BBs[0], BBs.size(), SwitchBB);
+
+ // Add a case for each block.
+ for (int i : llvm::seq<int>(1, BBs.size()))
+ SI->addCase(ConstantInt::get(CommonITy, i + 1), BBs[i]);
+
+ return true;
+}
Modified: stable/11/contrib/llvm/lib/CodeGen/TargetPassConfig.cpp
==============================================================================
--- stable/11/contrib/llvm/lib/CodeGen/TargetPassConfig.cpp Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/lib/CodeGen/TargetPassConfig.cpp Mon Mar 19 18:36:43 2018 (r331219)
@@ -790,6 +790,9 @@ void TargetPassConfig::addMachinePasses() {
if (EnableMachineOutliner)
PM->add(createMachineOutlinerPass());
+ // Add passes that directly emit MI after all other MI passes.
+ addPreEmitPass2();
+
AddingMachinePasses = false;
}
Modified: stable/11/contrib/llvm/lib/CodeGen/TargetSubtargetInfo.cpp
==============================================================================
--- stable/11/contrib/llvm/lib/CodeGen/TargetSubtargetInfo.cpp Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/lib/CodeGen/TargetSubtargetInfo.cpp Mon Mar 19 18:36:43 2018 (r331219)
@@ -37,6 +37,10 @@ bool TargetSubtargetInfo::enableAtomicExpand() const {
return true;
}
+bool TargetSubtargetInfo::enableIndirectBrExpand() const {
+ return false;
+}
+
bool TargetSubtargetInfo::enableMachineScheduler() const {
return false;
}
Modified: stable/11/contrib/llvm/lib/Target/X86/X86.h
==============================================================================
--- stable/11/contrib/llvm/lib/Target/X86/X86.h Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/lib/Target/X86/X86.h Mon Mar 19 18:36:43 2018 (r331219)
@@ -22,6 +22,7 @@ namespace llvm {
class FunctionPass;
class ImmutablePass;
class InstructionSelector;
+class ModulePass;
class PassRegistry;
class X86RegisterBankInfo;
class X86Subtarget;
@@ -97,6 +98,9 @@ void initializeFixupBWInstPassPass(PassRegistry &);
/// This pass replaces EVEX ecnoded of AVX-512 instructiosn by VEX
/// encoding when possible in order to reduce code size.
FunctionPass *createX86EvexToVexInsts();
+
+/// This pass creates the thunks for the retpoline feature.
+FunctionPass *createX86RetpolineThunksPass();
InstructionSelector *createX86InstructionSelector(const X86TargetMachine &TM,
X86Subtarget &,
Modified: stable/11/contrib/llvm/lib/Target/X86/X86.td
==============================================================================
--- stable/11/contrib/llvm/lib/Target/X86/X86.td Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/lib/Target/X86/X86.td Mon Mar 19 18:36:43 2018 (r331219)
@@ -290,6 +290,27 @@ def FeatureERMSB
"ermsb", "HasERMSB", "true",
"REP MOVS/STOS are fast">;
+// Enable mitigation of some aspects of speculative execution related
+// vulnerabilities by removing speculatable indirect branches. This disables
+// jump-table formation, rewrites explicit `indirectbr` instructions into
+// `switch` instructions, and uses a special construct called a "retpoline" to
+// prevent speculation of the remaining indirect branches (indirect calls and
+// tail calls).
+def FeatureRetpoline
+ : SubtargetFeature<"retpoline", "UseRetpoline", "true",
+ "Remove speculation of indirect branches from the "
+ "generated code, either by avoiding them entirely or "
+ "lowering them with a speculation blocking construct.">;
+
+// Rely on external thunks for the emitted retpoline calls. This allows users
+// to provide their own custom thunk definitions in highly specialized
+// environments such as a kernel that does boot-time hot patching.
+def FeatureRetpolineExternalThunk
+ : SubtargetFeature<
+ "retpoline-external-thunk", "UseRetpolineExternalThunk", "true",
+ "Enable retpoline, but with an externally provided thunk.",
+ [FeatureRetpoline]>;
+
//===----------------------------------------------------------------------===//
// X86 processors supported.
//===----------------------------------------------------------------------===//
Modified: stable/11/contrib/llvm/lib/Target/X86/X86AsmPrinter.cpp
==============================================================================
--- stable/11/contrib/llvm/lib/Target/X86/X86AsmPrinter.cpp Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/lib/Target/X86/X86AsmPrinter.cpp Mon Mar 19 18:36:43 2018 (r331219)
@@ -344,6 +344,8 @@ static void printIntelMemReference(X86AsmPrinter &P, c
static bool printAsmMRegister(X86AsmPrinter &P, const MachineOperand &MO,
char Mode, raw_ostream &O) {
unsigned Reg = MO.getReg();
+ bool EmitPercent = true;
+
switch (Mode) {
default: return true; // Unknown mode.
case 'b': // Print QImode register
@@ -358,6 +360,9 @@ static bool printAsmMRegister(X86AsmPrinter &P, const
case 'k': // Print SImode register
Reg = getX86SubSuperRegister(Reg, 32);
break;
+ case 'V':
+ EmitPercent = false;
+ LLVM_FALLTHROUGH;
case 'q':
// Print 64-bit register names if 64-bit integer registers are available.
// Otherwise, print 32-bit register names.
@@ -365,7 +370,10 @@ static bool printAsmMRegister(X86AsmPrinter &P, const
break;
}
- O << '%' << X86ATTInstPrinter::getRegisterName(Reg);
+ if (EmitPercent)
+ O << '%';
+
+ O << X86ATTInstPrinter::getRegisterName(Reg);
return false;
}
@@ -438,6 +446,7 @@ bool X86AsmPrinter::PrintAsmOperand(const MachineInstr
case 'w': // Print HImode register
case 'k': // Print SImode register
case 'q': // Print DImode register
+ case 'V': // Print native register without '%'
if (MO.isReg())
return printAsmMRegister(*this, MO, ExtraCode[0], O);
printOperand(*this, MI, OpNo, O);
Modified: stable/11/contrib/llvm/lib/Target/X86/X86AsmPrinter.h
==============================================================================
--- stable/11/contrib/llvm/lib/Target/X86/X86AsmPrinter.h Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/lib/Target/X86/X86AsmPrinter.h Mon Mar 19 18:36:43 2018 (r331219)
@@ -30,6 +30,7 @@ class LLVM_LIBRARY_VISIBILITY X86AsmPrinter : public A
StackMaps SM;
FaultMaps FM;
std::unique_ptr<MCCodeEmitter> CodeEmitter;
+ bool NeedsRetpoline = false;
// This utility class tracks the length of a stackmap instruction's 'shadow'.
// It is used by the X86AsmPrinter to ensure that the stackmap shadow
Modified: stable/11/contrib/llvm/lib/Target/X86/X86FastISel.cpp
==============================================================================
--- stable/11/contrib/llvm/lib/Target/X86/X86FastISel.cpp Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/lib/Target/X86/X86FastISel.cpp Mon Mar 19 18:36:43 2018 (r331219)
@@ -3161,6 +3161,10 @@ bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI)
(CalledFn && CalledFn->hasFnAttribute("no_caller_saved_registers")))
return false;
+ // Functions using retpoline should use SDISel for calls.
+ if (Subtarget->useRetpoline())
+ return false;
+
// Handle only C, fastcc, and webkit_js calling conventions for now.
switch (CC) {
default: return false;
Modified: stable/11/contrib/llvm/lib/Target/X86/X86FrameLowering.cpp
==============================================================================
--- stable/11/contrib/llvm/lib/Target/X86/X86FrameLowering.cpp Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/lib/Target/X86/X86FrameLowering.cpp Mon Mar 19 18:36:43 2018 (r331219)
@@ -742,6 +742,11 @@ void X86FrameLowering::emitStackProbeCall(MachineFunct
bool InProlog) const {
bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
+ // FIXME: Add retpoline support and remove this.
+ if (Is64Bit && IsLargeCodeModel && STI.useRetpoline())
+ report_fatal_error("Emitting stack probe calls on 64-bit with the large "
+ "code model and retpoline not yet implemented.");
+
unsigned CallOp;
if (Is64Bit)
CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
@@ -2337,6 +2342,10 @@ void X86FrameLowering::adjustForSegmentedStacks(
// This solution is not perfect, as it assumes that the .rodata section
// is laid out within 2^31 bytes of each function body, but this seems
// to be sufficient for JIT.
+ // FIXME: Add retpoline support and remove the error here..
+ if (STI.useRetpoline())
+ report_fatal_error("Emitting morestack calls on 64-bit with the large "
+ "code model and retpoline not yet implemented.");
BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
.addReg(X86::RIP)
.addImm(0)
Modified: stable/11/contrib/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
==============================================================================
--- stable/11/contrib/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Mar 19 18:36:43 2018 (r331219)
@@ -550,11 +550,11 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
SDNode *N = &*I++; // Preincrement iterator to avoid invalidation issues.
if (OptLevel != CodeGenOpt::None &&
- // Only does this when target favors doesn't favor register indirect
- // call.
+ // Only do this when the target can fold the load into the call or
+ // jmp.
+ !Subtarget->useRetpoline() &&
((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) ||
(N->getOpcode() == X86ISD::TC_RETURN &&
- // Only does this if load can be folded into TC_RETURN.
(Subtarget->is64Bit() ||
!getTargetMachine().isPositionIndependent())))) {
/// Also try moving call address load from outside callseq_start to just
Modified: stable/11/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp
==============================================================================
--- stable/11/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp Mon Mar 19 18:36:43 2018 (r331219)
@@ -24994,6 +24994,15 @@ X86TargetLowering::isVectorClearMaskLegal(const SmallV
return isShuffleMaskLegal(Mask, VT);
}
+bool X86TargetLowering::areJTsAllowed(const Function *Fn) const {
+ // If the subtarget is using retpolines, we need to not generate jump tables.
+ if (Subtarget.useRetpoline())
+ return false;
+
+ // Otherwise, fallback on the generic logic.
+ return TargetLowering::areJTsAllowed(Fn);
+}
+
//===----------------------------------------------------------------------===//
// X86 Scheduler Hooks
//===----------------------------------------------------------------------===//
@@ -26225,7 +26234,131 @@ X86TargetLowering::EmitLoweredTLSCall(MachineInstr &MI
return BB;
}
+static unsigned getOpcodeForRetpoline(unsigned RPOpc) {
+ switch (RPOpc) {
+ case X86::RETPOLINE_CALL32:
+ return X86::CALLpcrel32;
+ case X86::RETPOLINE_CALL64:
+ return X86::CALL64pcrel32;
+ case X86::RETPOLINE_TCRETURN32:
+ return X86::TCRETURNdi;
+ case X86::RETPOLINE_TCRETURN64:
+ return X86::TCRETURNdi64;
+ }
+ llvm_unreachable("not retpoline opcode");
+}
+
+static const char *getRetpolineSymbol(const X86Subtarget &Subtarget,
+ unsigned Reg) {
+ if (Subtarget.useRetpolineExternalThunk()) {
+ // When using an external thunk for retpolines, we pick names that match the
+ // names GCC happens to use as well. This helps simplify the implementation
+ // of the thunks for kernels where they have no easy ability to create
+ // aliases and are doing non-trivial configuration of the thunk's body. For
+ // example, the Linux kernel will do boot-time hot patching of the thunk
+ // bodies and cannot easily export aliases of these to loaded modules.
+ //
+ // Note that at any point in the future, we may need to change the semantics
+ // of how we implement retpolines and at that time will likely change the
+ // name of the called thunk. Essentially, there is no hard guarantee that
+ // LLVM will generate calls to specific thunks, we merely make a best-effort
+ // attempt to help out kernels and other systems where duplicating the
+ // thunks is costly.
+ switch (Reg) {
+ case X86::EAX:
+ assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
+ return "__x86_indirect_thunk_eax";
+ case X86::ECX:
+ assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
+ return "__x86_indirect_thunk_ecx";
+ case X86::EDX:
+ assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
+ return "__x86_indirect_thunk_edx";
+ case X86::EDI:
+ assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
+ return "__x86_indirect_thunk_edi";
+ case X86::R11:
+ assert(Subtarget.is64Bit() && "Should not be using a 64-bit thunk!");
+ return "__x86_indirect_thunk_r11";
+ }
+ llvm_unreachable("unexpected reg for retpoline");
+ }
+
+ // When targeting an internal COMDAT thunk use an LLVM-specific name.
+ switch (Reg) {
+ case X86::EAX:
+ assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
+ return "__llvm_retpoline_eax";
+ case X86::ECX:
+ assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
+ return "__llvm_retpoline_ecx";
+ case X86::EDX:
+ assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
+ return "__llvm_retpoline_edx";
+ case X86::EDI:
+ assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
+ return "__llvm_retpoline_edi";
+ case X86::R11:
+ assert(Subtarget.is64Bit() && "Should not be using a 64-bit thunk!");
+ return "__llvm_retpoline_r11";
+ }
+ llvm_unreachable("unexpected reg for retpoline");
+}
+
MachineBasicBlock *
+X86TargetLowering::EmitLoweredRetpoline(MachineInstr &MI,
+ MachineBasicBlock *BB) const {
+ // Copy the virtual register into the R11 physical register and
+ // call the retpoline thunk.
+ DebugLoc DL = MI.getDebugLoc();
+ const X86InstrInfo *TII = Subtarget.getInstrInfo();
+ unsigned CalleeVReg = MI.getOperand(0).getReg();
+ unsigned Opc = getOpcodeForRetpoline(MI.getOpcode());
+
+ // Find an available scratch register to hold the callee. On 64-bit, we can
+ // just use R11, but we scan for uses anyway to ensure we don't generate
+ // incorrect code. On 32-bit, we use one of EAX, ECX, or EDX that isn't
+ // already a register use operand to the call to hold the callee. If none
+ // are available, use EDI instead. EDI is chosen because EBX is the PIC base
+ // register and ESI is the base pointer to realigned stack frames with VLAs.
+ SmallVector<unsigned, 3> AvailableRegs;
+ if (Subtarget.is64Bit())
+ AvailableRegs.push_back(X86::R11);
+ else
+ AvailableRegs.append({X86::EAX, X86::ECX, X86::EDX, X86::EDI});
+
+ // Zero out any registers that are already used.
+ for (const auto &MO : MI.operands()) {
+ if (MO.isReg() && MO.isUse())
+ for (unsigned &Reg : AvailableRegs)
+ if (Reg == MO.getReg())
+ Reg = 0;
+ }
+
+ // Choose the first remaining non-zero available register.
+ unsigned AvailableReg = 0;
+ for (unsigned MaybeReg : AvailableRegs) {
+ if (MaybeReg) {
+ AvailableReg = MaybeReg;
+ break;
+ }
+ }
+ if (!AvailableReg)
+ report_fatal_error("calling convention incompatible with retpoline, no "
+ "available registers");
+
+ const char *Symbol = getRetpolineSymbol(Subtarget, AvailableReg);
+
+ BuildMI(*BB, MI, DL, TII->get(TargetOpcode::COPY), AvailableReg)
+ .addReg(CalleeVReg);
+ MI.getOperand(0).ChangeToES(Symbol);
+ MI.setDesc(TII->get(Opc));
+ MachineInstrBuilder(*BB->getParent(), &MI)
+ .addReg(AvailableReg, RegState::Implicit | RegState::Kill);
+ return BB;
+}
+
+MachineBasicBlock *
X86TargetLowering::emitEHSjLjSetJmp(MachineInstr &MI,
MachineBasicBlock *MBB) const {
DebugLoc DL = MI.getDebugLoc();
@@ -26689,6 +26822,11 @@ X86TargetLowering::EmitInstrWithCustomInserter(Machine
case X86::TLS_base_addr32:
case X86::TLS_base_addr64:
return EmitLoweredTLSAddr(MI, BB);
+ case X86::RETPOLINE_CALL32:
+ case X86::RETPOLINE_CALL64:
+ case X86::RETPOLINE_TCRETURN32:
+ case X86::RETPOLINE_TCRETURN64:
+ return EmitLoweredRetpoline(MI, BB);
case X86::CATCHRET:
return EmitLoweredCatchRet(MI, BB);
case X86::CATCHPAD:
Modified: stable/11/contrib/llvm/lib/Target/X86/X86ISelLowering.h
==============================================================================
--- stable/11/contrib/llvm/lib/Target/X86/X86ISelLowering.h Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/lib/Target/X86/X86ISelLowering.h Mon Mar 19 18:36:43 2018 (r331219)
@@ -986,6 +986,9 @@ namespace llvm {
bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
EVT VT) const override;
+ /// Returns true if lowering to a jump table is allowed.
+ bool areJTsAllowed(const Function *Fn) const override;
+
/// If true, then instruction selection should
/// seek to shrink the FP constant of the specified type to a smaller type
/// in order to save space and / or reduce runtime.
@@ -1288,6 +1291,9 @@ namespace llvm {
MachineBasicBlock *EmitLoweredTLSCall(MachineInstr &MI,
MachineBasicBlock *BB) const;
+
+ MachineBasicBlock *EmitLoweredRetpoline(MachineInstr &MI,
+ MachineBasicBlock *BB) const;
MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
MachineBasicBlock *MBB) const;
Modified: stable/11/contrib/llvm/lib/Target/X86/X86InstrCompiler.td
==============================================================================
--- stable/11/contrib/llvm/lib/Target/X86/X86InstrCompiler.td Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/lib/Target/X86/X86InstrCompiler.td Mon Mar 19 18:36:43 2018 (r331219)
@@ -1106,14 +1106,14 @@ def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off
def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
(TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
- Requires<[Not64BitMode]>;
+ Requires<[Not64BitMode, NotUseRetpoline]>;
// FIXME: This is disabled for 32-bit PIC mode because the global base
// register which is part of the address mode may be assigned a
// callee-saved register.
def : Pat<(X86tcret (load addr:$dst), imm:$off),
(TCRETURNmi addr:$dst, imm:$off)>,
- Requires<[Not64BitMode, IsNotPIC]>;
+ Requires<[Not64BitMode, IsNotPIC, NotUseRetpoline]>;
def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
(TCRETURNdi tglobaladdr:$dst, imm:$off)>,
@@ -1125,13 +1125,21 @@ def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off)
def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
(TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
- Requires<[In64BitMode]>;
+ Requires<[In64BitMode, NotUseRetpoline]>;
// Don't fold loads into X86tcret requiring more than 6 regs.
// There wouldn't be enough scratch registers for base+index.
def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
(TCRETURNmi64 addr:$dst, imm:$off)>,
- Requires<[In64BitMode]>;
+ Requires<[In64BitMode, NotUseRetpoline]>;
+
+def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
+ (RETPOLINE_TCRETURN64 ptr_rc_tailcall:$dst, imm:$off)>,
+ Requires<[In64BitMode, UseRetpoline]>;
+
+def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
+ (RETPOLINE_TCRETURN32 ptr_rc_tailcall:$dst, imm:$off)>,
+ Requires<[Not64BitMode, UseRetpoline]>;
def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
(TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
Modified: stable/11/contrib/llvm/lib/Target/X86/X86InstrControl.td
==============================================================================
--- stable/11/contrib/llvm/lib/Target/X86/X86InstrControl.td Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/lib/Target/X86/X86InstrControl.td Mon Mar 19 18:36:43 2018 (r331219)
@@ -211,11 +211,12 @@ let isCall = 1 in
Sched<[WriteJumpLd]>;
def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
"call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,
- OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
+ OpSize32, Requires<[Not64BitMode,NotUseRetpoline]>,
+ Sched<[WriteJump]>;
def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
"call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))],
IIC_CALL_MEM>, OpSize32,
- Requires<[Not64BitMode,FavorMemIndirectCall]>,
+ Requires<[Not64BitMode,FavorMemIndirectCall,NotUseRetpoline]>,
Sched<[WriteJumpLd]>;
let Predicates = [Not64BitMode] in {
@@ -298,11 +299,12 @@ let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in
def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
"call{q}\t{*}$dst", [(X86call GR64:$dst)],
IIC_CALL_RI>,
- Requires<[In64BitMode]>;
+ Requires<[In64BitMode,NotUseRetpoline]>;
def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst),
"call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))],
IIC_CALL_MEM>,
- Requires<[In64BitMode,FavorMemIndirectCall]>;
+ Requires<[In64BitMode,FavorMemIndirectCall,
+ NotUseRetpoline]>;
def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
"lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>;
@@ -338,6 +340,27 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarr
let mayLoad = 1 in
def TAILJMPm64_REX : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst),
"rex64 jmp{q}\t{*}$dst", [], IIC_JMP_MEM>;
+ }
+}
+
+let isPseudo = 1, isCall = 1, isCodeGenOnly = 1,
+ Uses = [RSP],
+ usesCustomInserter = 1,
+ SchedRW = [WriteJump] in {
+ def RETPOLINE_CALL32 :
+ PseudoI<(outs), (ins GR32:$dst), [(X86call GR32:$dst)]>,
+ Requires<[Not64BitMode,UseRetpoline]>;
+
+ def RETPOLINE_CALL64 :
+ PseudoI<(outs), (ins GR64:$dst), [(X86call GR64:$dst)]>,
+ Requires<[In64BitMode,UseRetpoline]>;
+
+ // Retpoline variant of indirect tail calls.
+ let isTerminator = 1, isReturn = 1, isBarrier = 1 in {
+ def RETPOLINE_TCRETURN64 :
+ PseudoI<(outs), (ins GR64:$dst, i32imm:$offset), []>;
+ def RETPOLINE_TCRETURN32 :
+ PseudoI<(outs), (ins GR32:$dst, i32imm:$offset), []>;
}
}
Modified: stable/11/contrib/llvm/lib/Target/X86/X86InstrInfo.td
==============================================================================
--- stable/11/contrib/llvm/lib/Target/X86/X86InstrInfo.td Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/lib/Target/X86/X86InstrInfo.td Mon Mar 19 18:36:43 2018 (r331219)
@@ -917,6 +917,8 @@ def HasFastLZCNT : Predicate<"Subtarget->hasFastLZCNT(
def HasFastSHLDRotate : Predicate<"Subtarget->hasFastSHLDRotate()">;
def HasERMSB : Predicate<"Subtarget->hasERMSB()">;
def HasMFence : Predicate<"Subtarget->hasMFence()">;
+def UseRetpoline : Predicate<"Subtarget->useRetpoline()">;
+def NotUseRetpoline : Predicate<"!Subtarget->useRetpoline()">;
//===----------------------------------------------------------------------===//
// X86 Instruction Format Definitions.
Modified: stable/11/contrib/llvm/lib/Target/X86/X86MCInstLower.cpp
==============================================================================
--- stable/11/contrib/llvm/lib/Target/X86/X86MCInstLower.cpp Mon Mar 19 18:34:08 2018 (r331218)
+++ stable/11/contrib/llvm/lib/Target/X86/X86MCInstLower.cpp Mon Mar 19 18:36:43 2018 (r331219)
@@ -874,6 +874,10 @@ void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr
// address is to far away. (TODO: support non-relative addressing)
break;
case MachineOperand::MO_Register:
+ // FIXME: Add retpoline support and remove this.
+ if (Subtarget->useRetpoline())
+ report_fatal_error("Lowering register statepoints with retpoline not "
+ "yet implemented.");
CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
CallOpcode = X86::CALL64r;
break;
@@ -1028,6 +1032,10 @@ void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr
EmitAndCountInstruction(
MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
+ // FIXME: Add retpoline support and remove this.
+ if (Subtarget->useRetpoline())
+ report_fatal_error(
+ "Lowering patchpoint with retpoline not yet implemented.");
EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
}
Added: stable/11/contrib/llvm/lib/Target/X86/X86RetpolineThunks.cpp
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ stable/11/contrib/llvm/lib/Target/X86/X86RetpolineThunks.cpp Mon Mar 19 18:36:43 2018 (r331219)
@@ -0,0 +1,265 @@
+//======- X86RetpolineThunks.cpp - Construct retpoline thunks for x86 --=====//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+/// \file
+///
+/// Pass that injects an MI thunk implementing a "retpoline". This is
+/// a RET-implemented trampoline that is used to lower indirect calls in a way
+/// that prevents speculation on some x86 processors and can be used to mitigate
+/// security vulnerabilities due to targeted speculative execution and side
+/// channels such as CVE-2017-5715.
+///
+/// TODO(chandlerc): All of this code could use better comments and
+/// documentation.
+///
+//===----------------------------------------------------------------------===//
+
+#include "X86.h"
+#include "X86InstrBuilder.h"
+#include "X86Subtarget.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/Instructions.h"
+#include "llvm/IR/Module.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "x86-retpoline-thunks"
+
+static const char ThunkNamePrefix[] = "__llvm_retpoline_";
+static const char R11ThunkName[] = "__llvm_retpoline_r11";
+static const char EAXThunkName[] = "__llvm_retpoline_eax";
+static const char ECXThunkName[] = "__llvm_retpoline_ecx";
+static const char EDXThunkName[] = "__llvm_retpoline_edx";
+static const char EDIThunkName[] = "__llvm_retpoline_edi";
+
+namespace {
+class X86RetpolineThunks : public MachineFunctionPass {
+public:
+ static char ID;
+
+ X86RetpolineThunks() : MachineFunctionPass(ID) {}
+
+ StringRef getPassName() const override { return "X86 Retpoline Thunks"; }
+
+ bool doInitialization(Module &M) override;
+ bool runOnMachineFunction(MachineFunction &F) override;
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ MachineFunctionPass::getAnalysisUsage(AU);
+ AU.addRequired<MachineModuleInfo>();
+ AU.addPreserved<MachineModuleInfo>();
+ }
+
+private:
+ MachineModuleInfo *MMI;
+ const TargetMachine *TM;
+ bool Is64Bit;
+ const X86Subtarget *STI;
+ const X86InstrInfo *TII;
+
+ bool InsertedThunks;
+
+ void createThunkFunction(Module &M, StringRef Name);
+ void insertRegReturnAddrClobber(MachineBasicBlock &MBB, unsigned Reg);
+ void populateThunk(MachineFunction &MF, Optional<unsigned> Reg = None);
+};
+
+} // end anonymous namespace
+
+FunctionPass *llvm::createX86RetpolineThunksPass() {
+ return new X86RetpolineThunks();
+}
+
+char X86RetpolineThunks::ID = 0;
+
+bool X86RetpolineThunks::doInitialization(Module &M) {
+ InsertedThunks = false;
+ return false;
+}
+
+bool X86RetpolineThunks::runOnMachineFunction(MachineFunction &MF) {
+ DEBUG(dbgs() << getPassName() << '\n');
+
+ TM = &MF.getTarget();;
+ STI = &MF.getSubtarget<X86Subtarget>();
+ TII = STI->getInstrInfo();
+ Is64Bit = TM->getTargetTriple().getArch() == Triple::x86_64;
+
+ MMI = &getAnalysis<MachineModuleInfo>();
+ Module &M = const_cast<Module &>(*MMI->getModule());
+
+ // If this function is not a thunk, check to see if we need to insert
+ // a thunk.
+ if (!MF.getName().startswith(ThunkNamePrefix)) {
+ // If we've already inserted a thunk, nothing else to do.
+ if (InsertedThunks)
+ return false;
+
+ // Only add a thunk if one of the functions has the retpoline feature
+ // enabled in its subtarget, and doesn't enable external thunks.
+ // FIXME: Conditionalize on indirect calls so we don't emit a thunk when
+ // nothing will end up calling it.
+ // FIXME: It's a little silly to look at every function just to enumerate
+ // the subtargets, but eventually we'll want to look at them for indirect
+ // calls, so maybe this is OK.
+ if (!STI->useRetpoline() || STI->useRetpolineExternalThunk())
+ return false;
+
+ // Otherwise, we need to insert the thunk.
+ // WARNING: This is not really a well behaving thing to do in a function
+ // pass. We extract the module and insert a new function (and machine
+ // function) directly into the module.
+ if (Is64Bit)
+ createThunkFunction(M, R11ThunkName);
+ else
+ for (StringRef Name :
+ {EAXThunkName, ECXThunkName, EDXThunkName, EDIThunkName})
+ createThunkFunction(M, Name);
+ InsertedThunks = true;
+ return true;
+ }
+
+ // If this *is* a thunk function, we need to populate it with the correct MI.
+ if (Is64Bit) {
+ assert(MF.getName() == "__llvm_retpoline_r11" &&
+ "Should only have an r11 thunk on 64-bit targets");
+
+ // __llvm_retpoline_r11:
+ // callq .Lr11_call_target
+ // .Lr11_capture_spec:
+ // pause
+ // lfence
+ // jmp .Lr11_capture_spec
+ // .align 16
+ // .Lr11_call_target:
+ // movq %r11, (%rsp)
+ // retq
+ populateThunk(MF, X86::R11);
+ } else {
+ // For 32-bit targets we need to emit a collection of thunks for various
+ // possible scratch registers as well as a fallback that uses EDI, which is
+ // normally callee saved.
+ // __llvm_retpoline_eax:
+ // calll .Leax_call_target
+ // .Leax_capture_spec:
+ // pause
+ // jmp .Leax_capture_spec
+ // .align 16
+ // .Leax_call_target:
+ // movl %eax, (%esp) # Clobber return addr
+ // retl
+ //
+ // __llvm_retpoline_ecx:
+ // ... # Same setup
+ // movl %ecx, (%esp)
+ // retl
+ //
+ // __llvm_retpoline_edx:
+ // ... # Same setup
+ // movl %edx, (%esp)
+ // retl
+ //
+ // __llvm_retpoline_edi:
+ // ... # Same setup
+ // movl %edi, (%esp)
+ // retl
+ if (MF.getName() == EAXThunkName)
+ populateThunk(MF, X86::EAX);
+ else if (MF.getName() == ECXThunkName)
+ populateThunk(MF, X86::ECX);
+ else if (MF.getName() == EDXThunkName)
+ populateThunk(MF, X86::EDX);
+ else if (MF.getName() == EDIThunkName)
+ populateThunk(MF, X86::EDI);
+ else
+ llvm_unreachable("Invalid thunk name on x86-32!");
+ }
+
+ return true;
+}
+
+void X86RetpolineThunks::createThunkFunction(Module &M, StringRef Name) {
+ assert(Name.startswith(ThunkNamePrefix) &&
+ "Created a thunk with an unexpected prefix!");
+
+ LLVMContext &Ctx = M.getContext();
+ auto Type = FunctionType::get(Type::getVoidTy(Ctx), false);
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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