svn commit: r335108 - head/sys/arm64/rockchip/clk

[Emmanuel Vadot]

On Thu, 14 Jun 2018 05:43:45 +0000 (UTC)
Emmanuel Vadot <manu at FreeBSD.org> wrote:

> Author: manu
> Date: Thu Jun 14 05:43:45 2018
> New Revision: 335108
> URL: https://svnweb.freebsd.org/changeset/base/335108
> 
> Log:
>   rk_pll: Add support for mode
>   
>   RockChip PLL have two modes controlled by a register, a "slow mode" (the
>   default one) where the frequency is derived from the 24Mhz oscillator on the
>   board, and a "normal" one when the pll take it's input from the real PLL output.
>   
>   Default the mode to normal for all the PLLs.
> 

 Thanks to jmcneill@ for the tip by the way.

-- 
Emmanuel Vadot <manu at bidouilliste.com> <manu at freebsd.org>