svn commit: r327790 - head/sys/mips/mips

[John Baldwin]

Author: jhb
Date: Wed Jan 10 21:08:43 2018
New Revision: 327790
URL: https://svnweb.freebsd.org/changeset/base/327790

Log:
  Set the 'FR' bit in the status register for N32 kernels.
  
  This permits N32 hard-float binaries to use 64-bit floating point
  registers (which is what N32 binaries expect) matching the N64 ABI.
  
  Reviewed by:	imp, jmallett
  Sponsored by:	DARPA / AFRL
  Differential Revision:	https://reviews.freebsd.org/D13830

Modified:
  head/sys/mips/mips/exception.S
  head/sys/mips/mips/locore.S
  head/sys/mips/mips/swtch.S
  head/sys/mips/mips/trap.c

Modified: head/sys/mips/mips/exception.S
==============================================================================
--- head/sys/mips/mips/exception.S	Wed Jan 10 21:05:46 2018	(r327789)
+++ head/sys/mips/mips/exception.S	Wed Jan 10 21:08:43 2018	(r327790)
@@ -1110,7 +1110,7 @@ NESTED(MipsFPTrap, CALLFRAME_SIZ, ra)
 	REG_S	ra, CALLFRAME_RA(sp)
 	.mask	0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
 
-#if defined(__mips_n64)
+#if defined(__mips_n32) || defined(__mips_n64)
 	or	t1, t0, MIPS_SR_COP_1_BIT | MIPS_SR_FR
 #else
 	or	t1, t0, MIPS_SR_COP_1_BIT

Modified: head/sys/mips/mips/locore.S
==============================================================================
--- head/sys/mips/mips/locore.S	Wed Jan 10 21:05:46 2018	(r327789)
+++ head/sys/mips/mips/locore.S	Wed Jan 10 21:08:43 2018	(r327790)
@@ -117,8 +117,11 @@ VECTOR(_locore, unknown)
 	 *	Enable FPU
 	 */
 	li	t1, MIPS_SR_COP_1_BIT
+#if defined(__mips_n32) || defined(__mips_n64)
+	or	t1, MIPS_SR_FR
+#endif
 #ifdef __mips_n64
-	or	t1, MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS_SR_FR
+	or	t1, MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX
 #endif
 #endif
 	/*

Modified: head/sys/mips/mips/swtch.S
==============================================================================
--- head/sys/mips/mips/swtch.S	Wed Jan 10 21:05:46 2018	(r327789)
+++ head/sys/mips/mips/swtch.S	Wed Jan 10 21:08:43 2018	(r327790)
@@ -416,7 +416,7 @@ LEAF(MipsSwitchFPState)
 	.set hardfloat
 	mfc0	t1, MIPS_COP_0_STATUS	# Save old SR
 	HAZARD_DELAY
-#if defined(__mips_n64)
+#if defined(__mips_n32) || defined(__mips_n64)
 	or	t0, t1, MIPS_SR_COP_1_BIT | MIPS_SR_FR	# enable the coprocessor
 #else
 	or	t0, t1, MIPS_SR_COP_1_BIT 		# enable the coprocessor
@@ -546,7 +546,7 @@ LEAF(MipsFPID)
 	.set hardfloat
 	mfc0	t1, MIPS_COP_0_STATUS		# Save the status register.
 	HAZARD_DELAY
-#if defined(__mips_n64)
+#if defined(__mips_n32) || defined(__mips_n64)
 	or	t0, t1, MIPS_SR_COP_1_BIT | MIPS_SR_FR
 #else
 	or	t0, t1, MIPS_SR_COP_1_BIT
@@ -585,7 +585,7 @@ LEAF(MipsSaveCurFPState)
 	PTR_L	a0, TD_PCB(a0)			# get pointer to pcb for thread
 	mfc0	t1, MIPS_COP_0_STATUS		# Disable interrupts and
 	HAZARD_DELAY
-#if defined(__mips_n64)
+#if defined(__mips_n32) || defined(__mips_n64)
 	or	t0, t1, MIPS_SR_COP_1_BIT | MIPS_SR_FR		#  enable the coprocessor
 #else
 	or	t0, t1, MIPS_SR_COP_1_BIT 			#  enable the coprocessor

Modified: head/sys/mips/mips/trap.c
==============================================================================
--- head/sys/mips/mips/trap.c	Wed Jan 10 21:05:46 2018	(r327789)
+++ head/sys/mips/mips/trap.c	Wed Jan 10 21:08:43 2018	(r327790)
@@ -983,7 +983,7 @@ dofault:
 			addr = trapframe->pc;
 			MipsSwitchFPState(PCPU_GET(fpcurthread), td->td_frame);
 			PCPU_SET(fpcurthread, td);
-#if defined(__mips_n64)
+#if defined(__mips_n32) || defined(__mips_n64)
 			td->td_frame->sr |= MIPS_SR_COP_1_BIT | MIPS_SR_FR;
 #else
 			td->td_frame->sr |= MIPS_SR_COP_1_BIT;