svn commit: r337137 - in vendor/llvm/dist: cmake/modules docs docs/CommandGuide include/llvm include/llvm/ADT include/llvm/Analysis include/llvm/BinaryFormat include/llvm/CodeGen include/llvm/CodeG...
Dimitry Andric
dim at FreeBSD.org
Thu Aug 2 17:32:53 UTC 2018
Author: dim
Date: Thu Aug 2 17:32:43 2018
New Revision: 337137
URL: https://svnweb.freebsd.org/changeset/base/337137
Log:
Vendor import of llvm trunk r338536:
https://llvm.org/svn/llvm-project/llvm/trunk@338536
Added:
vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFDebugAddr.h (contents, props changed)
vendor/llvm/dist/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp (contents, props changed)
vendor/llvm/dist/lib/Transforms/Vectorize/VPlanDominatorTree.h (contents, props changed)
vendor/llvm/dist/lib/Transforms/Vectorize/VPlanLoopInfo.h (contents, props changed)
vendor/llvm/dist/test/Analysis/BasicAA/phi-values-usage.ll
vendor/llvm/dist/test/CodeGen/AArch64/GlobalISel/irtranslator-block-order.ll
vendor/llvm/dist/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
vendor/llvm/dist/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
vendor/llvm/dist/test/CodeGen/AArch64/machine-outliner-default.mir
vendor/llvm/dist/test/CodeGen/AArch64/machine-outliner-regsave.mir
vendor/llvm/dist/test/CodeGen/AMDGPU/fmaxnum.r600.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/fminnum.r600.ll
vendor/llvm/dist/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.ltolz.ll
vendor/llvm/dist/test/CodeGen/Hexagon/bit-cmp0.mir
vendor/llvm/dist/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir
vendor/llvm/dist/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll
vendor/llvm/dist/test/CodeGen/Mips/GlobalISel/legalizer/global_address.mir
vendor/llvm/dist/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address.ll
vendor/llvm/dist/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir
vendor/llvm/dist/test/CodeGen/X86/pmaddubsw.ll
vendor/llvm/dist/test/CodeGen/X86/win_coreclr_chkstk_liveins.mir
vendor/llvm/dist/test/DebugInfo/PDB/pdb-invalid-type.test
vendor/llvm/dist/test/DebugInfo/PDB/using-namespace.test
vendor/llvm/dist/test/DebugInfo/RISCV/
vendor/llvm/dist/test/DebugInfo/RISCV/lit.local.cfg
vendor/llvm/dist/test/DebugInfo/RISCV/relax-debug-line.ll
vendor/llvm/dist/test/DebugInfo/X86/debug_addr.ll
vendor/llvm/dist/test/Demangle/ms-cxx11.test
vendor/llvm/dist/test/Demangle/ms-nested-scopes.test
vendor/llvm/dist/test/Demangle/ms-return-qualifiers.test
vendor/llvm/dist/test/Demangle/ms-template-callback.test
vendor/llvm/dist/test/MC/AArch64/SVE/brka-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/brka.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/brkas-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/brkas.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/brkb-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/brkb.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/brkbs-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/brkbs.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/brkn-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/brkn.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/brkns-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/brkns.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/brkpa-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/brkpa.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/brkpas-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/brkpas.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/brkpb-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/brkpb.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/brkpbs-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/brkpbs.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/ctermeq-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/ctermeq.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/ctermne-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/ctermne.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/movprfx-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/movprfx.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/pfalse-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/pfalse.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/pfirst-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/pfirst.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/pnext-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/pnext.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/ptest-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/ptest.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/rev-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/sel-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/uqdecp-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/whilele-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/whilele.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/whilelo-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/whilelo.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/whilels-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/whilels.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/whilelt-diagnostics.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/SVE/whilelt.s (contents, props changed)
vendor/llvm/dist/test/MC/AArch64/inst-directive-other.s (contents, props changed)
vendor/llvm/dist/test/MC/ARM/inst-directive-other.s (contents, props changed)
vendor/llvm/dist/test/MC/ARM/inst-thumb-suffixes-auto.s (contents, props changed)
vendor/llvm/dist/test/Transforms/GlobalOpt/globalsra-multigep.ll
vendor/llvm/dist/test/Transforms/InstCombine/pow-cbrt.ll
vendor/llvm/dist/test/Transforms/InstCombine/select-binop-icmp.ll
vendor/llvm/dist/test/Transforms/InstSimplify/select-and-cmp.ll
vendor/llvm/dist/test/Transforms/InstSimplify/select-or-cmp.ll
vendor/llvm/dist/test/Transforms/SLPVectorizer/AArch64/PR38339.ll
vendor/llvm/dist/test/tools/llvm-dwarfdump/X86/debug_addr.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-dwarfdump/X86/debug_addr_64bit_address.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-dwarfdump/X86/debug_addr_absent.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-dwarfdump/X86/debug_addr_address_size_mismatch.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-dwarfdump/X86/debug_addr_address_size_not_multiple.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-dwarfdump/X86/debug_addr_dwarf4.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-dwarfdump/X86/debug_addr_dwarf64.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-dwarfdump/X86/debug_addr_empty.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-dwarfdump/X86/debug_addr_invalid_addr_size.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-dwarfdump/X86/debug_addr_segment_selector.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-dwarfdump/X86/debug_addr_small_length_field.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_length_field.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_section.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-dwarfdump/X86/debug_addr_unsupported_version.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-dwarfdump/X86/debug_addr_version_mismatch.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-mca/X86/Atom/resources-x86_32.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-mca/X86/Broadwell/resources-x86_32.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-mca/X86/BtVer2/resources-x86_32.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-mca/X86/Generic/resources-x86_32.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-mca/X86/Haswell/resources-x86_32.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-mca/X86/SLM/resources-x86_32.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-mca/X86/SandyBridge/resources-x86_32.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-mca/X86/SkylakeClient/resources-x86_32.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-mca/X86/SkylakeServer/resources-x86_32.s (contents, props changed)
vendor/llvm/dist/test/tools/llvm-mca/X86/Znver1/resources-x86_32.s (contents, props changed)
vendor/llvm/dist/unittests/Transforms/Vectorize/VPlanDominatorTreeTest.cpp (contents, props changed)
vendor/llvm/dist/unittests/Transforms/Vectorize/VPlanLoopInfoTest.cpp (contents, props changed)
Deleted:
vendor/llvm/dist/tools/llvm-mca/README.txt
Modified:
vendor/llvm/dist/cmake/modules/AddLLVM.cmake
vendor/llvm/dist/docs/CommandGuide/llvm-mca.rst
vendor/llvm/dist/docs/GettingStarted.rst
vendor/llvm/dist/docs/LangRef.rst
vendor/llvm/dist/docs/SourceLevelDebugging.rst
vendor/llvm/dist/include/llvm/ADT/DenseSet.h
vendor/llvm/dist/include/llvm/Analysis/BasicAliasAnalysis.h
vendor/llvm/dist/include/llvm/Analysis/LoopAccessAnalysis.h
vendor/llvm/dist/include/llvm/Analysis/MemoryDependenceAnalysis.h
vendor/llvm/dist/include/llvm/Analysis/MustExecute.h
vendor/llvm/dist/include/llvm/Analysis/TargetTransformInfoImpl.h
vendor/llvm/dist/include/llvm/Analysis/ValueTracking.h
vendor/llvm/dist/include/llvm/BinaryFormat/Dwarf.def
vendor/llvm/dist/include/llvm/BinaryFormat/ELF.h
vendor/llvm/dist/include/llvm/CodeGen/GCStrategy.h
vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
vendor/llvm/dist/include/llvm/CodeGen/MachORelocation.h
vendor/llvm/dist/include/llvm/CodeGen/MachineModuleInfo.h
vendor/llvm/dist/include/llvm/CodeGen/MachineOutliner.h
vendor/llvm/dist/include/llvm/CodeGen/ScheduleDAG.h
vendor/llvm/dist/include/llvm/CodeGen/StackMaps.h
vendor/llvm/dist/include/llvm/CodeGen/TargetLowering.h
vendor/llvm/dist/include/llvm/CodeGen/TargetPassConfig.h
vendor/llvm/dist/include/llvm/CodeGen/TargetRegisterInfo.h
vendor/llvm/dist/include/llvm/DebugInfo/CodeView/CodeViewSymbols.def
vendor/llvm/dist/include/llvm/DebugInfo/CodeView/SymbolRecord.h
vendor/llvm/dist/include/llvm/DebugInfo/DIContext.h
vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFContext.h
vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFDataExtractor.h
vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFDie.h
vendor/llvm/dist/include/llvm/ExecutionEngine/Orc/RPCSerialization.h
vendor/llvm/dist/include/llvm/IR/Attributes.td
vendor/llvm/dist/include/llvm/IR/Instruction.h
vendor/llvm/dist/include/llvm/IR/Instructions.h
vendor/llvm/dist/include/llvm/IR/Intrinsics.td
vendor/llvm/dist/include/llvm/IR/IntrinsicsAMDGPU.td
vendor/llvm/dist/include/llvm/IR/IntrinsicsARM.td
vendor/llvm/dist/include/llvm/IR/IntrinsicsPowerPC.td
vendor/llvm/dist/include/llvm/IR/LegacyPassManagers.h
vendor/llvm/dist/include/llvm/IR/Statepoint.h
vendor/llvm/dist/include/llvm/IR/User.h
vendor/llvm/dist/include/llvm/LinkAllIR.h
vendor/llvm/dist/include/llvm/MC/MCDwarf.h
vendor/llvm/dist/include/llvm/MC/MCFragment.h
vendor/llvm/dist/include/llvm/MC/MCInstrAnalysis.h
vendor/llvm/dist/include/llvm/MC/MCParser/AsmCond.h
vendor/llvm/dist/include/llvm/MC/MCStreamer.h
vendor/llvm/dist/include/llvm/Object/MachO.h
vendor/llvm/dist/include/llvm/PassAnalysisSupport.h
vendor/llvm/dist/include/llvm/PassRegistry.h
vendor/llvm/dist/include/llvm/ProfileData/Coverage/CoverageMapping.h
vendor/llvm/dist/include/llvm/Support/ARMBuildAttributes.h
vendor/llvm/dist/include/llvm/Support/DataExtractor.h
vendor/llvm/dist/include/llvm/Support/GenericDomTree.h
vendor/llvm/dist/include/llvm/Support/MemoryBuffer.h
vendor/llvm/dist/include/llvm/Support/SmallVectorMemoryBuffer.h
vendor/llvm/dist/include/llvm/Support/TargetOpcodes.def
vendor/llvm/dist/include/llvm/Support/xxhash.h
vendor/llvm/dist/include/llvm/Target/GenericOpcodes.td
vendor/llvm/dist/include/llvm/Target/TargetCallingConv.td
vendor/llvm/dist/include/llvm/Target/TargetInstrPredicate.td
vendor/llvm/dist/include/llvm/Transforms/Scalar/SpeculativeExecution.h
vendor/llvm/dist/include/llvm/Transforms/Utils/CodeExtractor.h
vendor/llvm/dist/include/llvm/Transforms/Utils/FunctionComparator.h
vendor/llvm/dist/include/llvm/Transforms/Utils/SymbolRewriter.h
vendor/llvm/dist/lib/Analysis/AliasSetTracker.cpp
vendor/llvm/dist/lib/Analysis/BasicAliasAnalysis.cpp
vendor/llvm/dist/lib/Analysis/CFGPrinter.cpp
vendor/llvm/dist/lib/Analysis/CallGraph.cpp
vendor/llvm/dist/lib/Analysis/CallGraphSCCPass.cpp
vendor/llvm/dist/lib/Analysis/DemandedBits.cpp
vendor/llvm/dist/lib/Analysis/GlobalsModRef.cpp
vendor/llvm/dist/lib/Analysis/InstructionSimplify.cpp
vendor/llvm/dist/lib/Analysis/LazyValueInfo.cpp
vendor/llvm/dist/lib/Analysis/LoopAccessAnalysis.cpp
vendor/llvm/dist/lib/Analysis/MemDepPrinter.cpp
vendor/llvm/dist/lib/Analysis/MemoryDependenceAnalysis.cpp
vendor/llvm/dist/lib/Analysis/MustExecute.cpp
vendor/llvm/dist/lib/Analysis/ScalarEvolution.cpp
vendor/llvm/dist/lib/Analysis/TargetTransformInfo.cpp
vendor/llvm/dist/lib/Analysis/ValueTracking.cpp
vendor/llvm/dist/lib/AsmParser/LLParser.cpp
vendor/llvm/dist/lib/Bitcode/Writer/BitcodeWriter.cpp
vendor/llvm/dist/lib/CodeGen/AntiDepBreaker.h
vendor/llvm/dist/lib/CodeGen/AsmPrinter/AddressPool.cpp
vendor/llvm/dist/lib/CodeGen/AsmPrinter/AddressPool.h
vendor/llvm/dist/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
vendor/llvm/dist/lib/CodeGen/AsmPrinter/DwarfDebug.h
vendor/llvm/dist/lib/CodeGen/AsmPrinter/DwarfExpression.h
vendor/llvm/dist/lib/CodeGen/AsmPrinter/DwarfFile.cpp
vendor/llvm/dist/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
vendor/llvm/dist/lib/CodeGen/AtomicExpandPass.cpp
vendor/llvm/dist/lib/CodeGen/BuiltinGCs.cpp
vendor/llvm/dist/lib/CodeGen/CriticalAntiDepBreaker.cpp
vendor/llvm/dist/lib/CodeGen/GCMetadata.cpp
vendor/llvm/dist/lib/CodeGen/GlobalISel/IRTranslator.cpp
vendor/llvm/dist/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
vendor/llvm/dist/lib/CodeGen/GlobalMerge.cpp
vendor/llvm/dist/lib/CodeGen/IntrinsicLowering.cpp
vendor/llvm/dist/lib/CodeGen/LiveDebugValues.cpp
vendor/llvm/dist/lib/CodeGen/MachineModuleInfo.cpp
vendor/llvm/dist/lib/CodeGen/MachineOutliner.cpp
vendor/llvm/dist/lib/CodeGen/MachineRegisterInfo.cpp
vendor/llvm/dist/lib/CodeGen/MachineSSAUpdater.cpp
vendor/llvm/dist/lib/CodeGen/MachineSink.cpp
vendor/llvm/dist/lib/CodeGen/MachineTraceMetrics.cpp
vendor/llvm/dist/lib/CodeGen/MachineVerifier.cpp
vendor/llvm/dist/lib/CodeGen/RegisterScavenging.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/FastISel.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeTypes.h
vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
vendor/llvm/dist/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/TargetLowering.cpp
vendor/llvm/dist/lib/CodeGen/ShadowStackGCLowering.cpp
vendor/llvm/dist/lib/CodeGen/SplitKit.h
vendor/llvm/dist/lib/CodeGen/TargetLoweringBase.cpp
vendor/llvm/dist/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
vendor/llvm/dist/lib/CodeGen/TargetPassConfig.cpp
vendor/llvm/dist/lib/CodeGen/WinEHPrepare.cpp
vendor/llvm/dist/lib/DebugInfo/CodeView/RecordName.cpp
vendor/llvm/dist/lib/DebugInfo/CodeView/SymbolDumper.cpp
vendor/llvm/dist/lib/DebugInfo/CodeView/SymbolRecordMapping.cpp
vendor/llvm/dist/lib/DebugInfo/CodeView/TypeIndexDiscovery.cpp
vendor/llvm/dist/lib/DebugInfo/CodeView/TypeStreamMerger.cpp
vendor/llvm/dist/lib/DebugInfo/DWARF/CMakeLists.txt
vendor/llvm/dist/lib/DebugInfo/DWARF/DWARFAbbreviationDeclaration.cpp
vendor/llvm/dist/lib/DebugInfo/DWARF/DWARFContext.cpp
vendor/llvm/dist/lib/DebugInfo/Symbolize/SymbolizableObjectFile.cpp
vendor/llvm/dist/lib/Demangle/ItaniumDemangle.cpp
vendor/llvm/dist/lib/Demangle/MicrosoftDemangle.cpp
vendor/llvm/dist/lib/Demangle/StringView.h
vendor/llvm/dist/lib/ExecutionEngine/ExecutionEngineBindings.cpp
vendor/llvm/dist/lib/ExecutionEngine/IntelJITEvents/ittnotify_config.h
vendor/llvm/dist/lib/ExecutionEngine/IntelJITEvents/jitprofiling.h
vendor/llvm/dist/lib/ExecutionEngine/Interpreter/Execution.cpp
vendor/llvm/dist/lib/ExecutionEngine/Interpreter/Interpreter.h
vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/RTDyldMemoryManager.cpp
vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
vendor/llvm/dist/lib/FuzzMutate/FuzzerCLI.cpp
vendor/llvm/dist/lib/IR/Attributes.cpp
vendor/llvm/dist/lib/IR/AutoUpgrade.cpp
vendor/llvm/dist/lib/IR/Function.cpp
vendor/llvm/dist/lib/IR/InlineAsm.cpp
vendor/llvm/dist/lib/IR/Instructions.cpp
vendor/llvm/dist/lib/IR/LLVMContextImpl.h
vendor/llvm/dist/lib/IR/SymbolTableListTraitsImpl.h
vendor/llvm/dist/lib/IR/ValueSymbolTable.cpp
vendor/llvm/dist/lib/LTO/ThinLTOCodeGenerator.cpp
vendor/llvm/dist/lib/MC/MCAsmStreamer.cpp
vendor/llvm/dist/lib/MC/MCAssembler.cpp
vendor/llvm/dist/lib/MC/MCDisassembler/Disassembler.cpp
vendor/llvm/dist/lib/MC/MCDisassembler/Disassembler.h
vendor/llvm/dist/lib/MC/MCDwarf.cpp
vendor/llvm/dist/lib/MC/MCInstrAnalysis.cpp
vendor/llvm/dist/lib/MC/MCObjectFileInfo.cpp
vendor/llvm/dist/lib/MC/MCParser/ELFAsmParser.cpp
vendor/llvm/dist/lib/MC/MCStreamer.cpp
vendor/llvm/dist/lib/MC/MachObjectWriter.cpp
vendor/llvm/dist/lib/Object/COFFObjectFile.cpp
vendor/llvm/dist/lib/ObjectYAML/CodeViewYAMLSymbols.cpp
vendor/llvm/dist/lib/Support/APFloat.cpp
vendor/llvm/dist/lib/Support/ConvertUTF.cpp
vendor/llvm/dist/lib/Support/CrashRecoveryContext.cpp
vendor/llvm/dist/lib/Support/DAGDeltaAlgorithm.cpp
vendor/llvm/dist/lib/Support/Errno.cpp
vendor/llvm/dist/lib/Support/FoldingSet.cpp
vendor/llvm/dist/lib/Support/FormattedStream.cpp
vendor/llvm/dist/lib/Support/ManagedStatic.cpp
vendor/llvm/dist/lib/Support/MemoryBuffer.cpp
vendor/llvm/dist/lib/Support/Path.cpp
vendor/llvm/dist/lib/Support/PrettyStackTrace.cpp
vendor/llvm/dist/lib/Support/SourceMgr.cpp
vendor/llvm/dist/lib/Support/StringPool.cpp
vendor/llvm/dist/lib/Support/StringRef.cpp
vendor/llvm/dist/lib/Support/TargetRegistry.cpp
vendor/llvm/dist/lib/Support/Windows/Path.inc
vendor/llvm/dist/lib/Support/YAMLParser.cpp
vendor/llvm/dist/lib/Support/regex_impl.h
vendor/llvm/dist/lib/Support/xxhash.cpp
vendor/llvm/dist/lib/TableGen/StringMatcher.cpp
vendor/llvm/dist/lib/Target/AArch64/AArch64FastISel.cpp
vendor/llvm/dist/lib/Target/AArch64/AArch64ISelLowering.cpp
vendor/llvm/dist/lib/Target/AArch64/AArch64ISelLowering.h
vendor/llvm/dist/lib/Target/AArch64/AArch64InstrFormats.td
vendor/llvm/dist/lib/Target/AArch64/AArch64InstrInfo.cpp
vendor/llvm/dist/lib/Target/AArch64/AArch64InstrInfo.h
vendor/llvm/dist/lib/Target/AArch64/AArch64InstructionSelector.cpp
vendor/llvm/dist/lib/Target/AArch64/AArch64LegalizerInfo.cpp
vendor/llvm/dist/lib/Target/AArch64/AArch64MachineFunctionInfo.h
vendor/llvm/dist/lib/Target/AArch64/AArch64RegisterInfo.td
vendor/llvm/dist/lib/Target/AArch64/AArch64SVEInstrInfo.td
vendor/llvm/dist/lib/Target/AArch64/AArch64TargetMachine.cpp
vendor/llvm/dist/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
vendor/llvm/dist/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
vendor/llvm/dist/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
vendor/llvm/dist/lib/Target/AArch64/SVEInstrFormats.td
vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUInstrInfo.td
vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUInstructions.td
vendor/llvm/dist/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
vendor/llvm/dist/lib/Target/AMDGPU/MIMGInstructions.td
vendor/llvm/dist/lib/Target/AMDGPU/SIISelLowering.cpp
vendor/llvm/dist/lib/Target/AMDGPU/SIISelLowering.h
vendor/llvm/dist/lib/Target/AMDGPU/SIInsertSkips.cpp
vendor/llvm/dist/lib/Target/AMDGPU/SIInstrInfo.cpp
vendor/llvm/dist/lib/Target/AMDGPU/SIInstrInfo.h
vendor/llvm/dist/lib/Target/AMDGPU/SIInstructions.td
vendor/llvm/dist/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
vendor/llvm/dist/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
vendor/llvm/dist/lib/Target/AMDGPU/VOP3PInstructions.td
vendor/llvm/dist/lib/Target/ARM/ARMAsmPrinter.cpp
vendor/llvm/dist/lib/Target/ARM/ARMBaseRegisterInfo.cpp
vendor/llvm/dist/lib/Target/ARM/ARMCallingConv.h
vendor/llvm/dist/lib/Target/ARM/ARMConstantIslandPass.cpp
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vendor/llvm/dist/test/MC/AArch64/SVE/sdiv.s
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vendor/llvm/dist/test/MC/AArch64/SVE/smax-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/smax.s
vendor/llvm/dist/test/MC/AArch64/SVE/smaxv-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/smin-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/smin.s
vendor/llvm/dist/test/MC/AArch64/SVE/sminv-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/smulh.s
vendor/llvm/dist/test/MC/AArch64/SVE/splice-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/splice.s
vendor/llvm/dist/test/MC/AArch64/SVE/sqadd-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/sqadd.s
vendor/llvm/dist/test/MC/AArch64/SVE/sqdecd-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/sqdecd.s
vendor/llvm/dist/test/MC/AArch64/SVE/sqdech-diagnostics.s
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vendor/llvm/dist/test/MC/AArch64/SVE/sqdecp-diagnostics.s
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vendor/llvm/dist/test/MC/AArch64/SVE/sqincd-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/sqincd.s
vendor/llvm/dist/test/MC/AArch64/SVE/sqinch-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/sqinch.s
vendor/llvm/dist/test/MC/AArch64/SVE/sqincp-diagnostics.s
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vendor/llvm/dist/test/MC/AArch64/SVE/sqincw.s
vendor/llvm/dist/test/MC/AArch64/SVE/sqsub-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/sqsub.s
vendor/llvm/dist/test/MC/AArch64/SVE/st1b-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/st1d-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/st1h-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/st1w-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/st2b-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/st2d-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/st2h-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/st2w-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/st3b-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/st3d-diagnostics.s
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vendor/llvm/dist/test/MC/AArch64/SVE/st3w-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/st4b-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/st4d-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/st4h-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/st4w-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/stnt1b-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/stnt1d-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/stnt1h-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/stnt1w-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/sub-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/sub.s
vendor/llvm/dist/test/MC/AArch64/SVE/subr-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/subr.s
vendor/llvm/dist/test/MC/AArch64/SVE/sunpkhi-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/sunpklo-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/sxtb.s
vendor/llvm/dist/test/MC/AArch64/SVE/sxth.s
vendor/llvm/dist/test/MC/AArch64/SVE/sxtw.s
vendor/llvm/dist/test/MC/AArch64/SVE/tbl-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/trn1-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/trn2-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/uabd.s
vendor/llvm/dist/test/MC/AArch64/SVE/uaddv-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/ucvtf.s
vendor/llvm/dist/test/MC/AArch64/SVE/udiv.s
vendor/llvm/dist/test/MC/AArch64/SVE/udivr.s
vendor/llvm/dist/test/MC/AArch64/SVE/udot-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/udot.s
vendor/llvm/dist/test/MC/AArch64/SVE/umax-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/umax.s
vendor/llvm/dist/test/MC/AArch64/SVE/umaxv-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/umin-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/umin.s
vendor/llvm/dist/test/MC/AArch64/SVE/uminv-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/umulh.s
vendor/llvm/dist/test/MC/AArch64/SVE/uqadd-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/uqadd.s
vendor/llvm/dist/test/MC/AArch64/SVE/uqdecd-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/uqdecd.s
vendor/llvm/dist/test/MC/AArch64/SVE/uqdech-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/uqdech.s
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vendor/llvm/dist/test/MC/AArch64/SVE/uqincd-diagnostics.s
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vendor/llvm/dist/test/MC/AArch64/SVE/uqinch-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/uqinch.s
vendor/llvm/dist/test/MC/AArch64/SVE/uqincp-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/uqincp.s
vendor/llvm/dist/test/MC/AArch64/SVE/uqincw-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/uqincw.s
vendor/llvm/dist/test/MC/AArch64/SVE/uqsub-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/uqsub.s
vendor/llvm/dist/test/MC/AArch64/SVE/uunpkhi-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/uunpklo-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/uxtb.s
vendor/llvm/dist/test/MC/AArch64/SVE/uxth.s
vendor/llvm/dist/test/MC/AArch64/SVE/uxtw.s
vendor/llvm/dist/test/MC/AArch64/SVE/uzp1-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/uzp2-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/zip1-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/SVE/zip2-diagnostics.s
vendor/llvm/dist/test/MC/AArch64/arm64-directive_loh.s
vendor/llvm/dist/test/MC/ARM/directive-unsupported.s
vendor/llvm/dist/test/MC/ARM/inst-thumb-suffixes.s
vendor/llvm/dist/test/MC/WebAssembly/debug-info.ll
vendor/llvm/dist/test/Other/new-pm-defaults.ll
vendor/llvm/dist/test/Other/new-pm-lto-defaults.ll
vendor/llvm/dist/test/Other/new-pm-thinlto-defaults.ll
vendor/llvm/dist/test/Other/opt-O2-pipeline.ll
vendor/llvm/dist/test/Other/opt-O3-pipeline.ll
vendor/llvm/dist/test/Other/opt-Os-pipeline.ll
vendor/llvm/dist/test/Transforms/GVN/PRE/pre-after-rle.ll
vendor/llvm/dist/test/Transforms/GlobalOpt/globalsra-partial.ll
vendor/llvm/dist/test/Transforms/Inline/attributes.ll
vendor/llvm/dist/test/Transforms/InstCombine/and-xor-or.ll
vendor/llvm/dist/test/Transforms/InstCombine/and2.ll
vendor/llvm/dist/test/Transforms/InstCombine/double-float-shrink-1.ll
vendor/llvm/dist/test/Transforms/InstCombine/gep-addrspace.ll
vendor/llvm/dist/test/Transforms/InstCombine/pow-1.ll
vendor/llvm/dist/test/Transforms/InstCombine/pow-sqrt.ll
vendor/llvm/dist/test/Transforms/InstCombine/sub-not.ll
vendor/llvm/dist/test/Transforms/InstCombine/xor.ll
vendor/llvm/dist/test/Transforms/InstSimplify/AndOrXor.ll
vendor/llvm/dist/test/Transforms/InstSimplify/call.ll
vendor/llvm/dist/test/Transforms/InstSimplify/shift.ll
vendor/llvm/dist/test/Transforms/LCSSA/basictest.ll
vendor/llvm/dist/test/Transforms/SCCP/preserve-analysis.ll
vendor/llvm/dist/test/Transforms/SimplifyCFG/merge-cond-stores.ll
vendor/llvm/dist/test/tools/dsymutil/X86/accelerator.test
vendor/llvm/dist/test/tools/dsymutil/X86/update-one-CU.test
vendor/llvm/dist/test/tools/dsymutil/X86/update.test
vendor/llvm/dist/test/tools/llvm-mca/X86/Atom/resources-x86_64.s
vendor/llvm/dist/test/tools/llvm-mca/X86/Broadwell/resources-x86_64.s
vendor/llvm/dist/test/tools/llvm-mca/X86/BtVer2/dependency-breaking-cmp.s
vendor/llvm/dist/test/tools/llvm-mca/X86/BtVer2/dependency-breaking-pcmpeq.s
vendor/llvm/dist/test/tools/llvm-mca/X86/BtVer2/dependency-breaking-sbb-2.s
vendor/llvm/dist/test/tools/llvm-mca/X86/BtVer2/one-idioms.s
vendor/llvm/dist/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s
vendor/llvm/dist/test/tools/llvm-mca/X86/Generic/resources-x86_64.s
vendor/llvm/dist/test/tools/llvm-mca/X86/Haswell/resources-x86_64.s
vendor/llvm/dist/test/tools/llvm-mca/X86/SLM/resources-x86_64.s
vendor/llvm/dist/test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s
vendor/llvm/dist/test/tools/llvm-mca/X86/SkylakeClient/resources-x86_64.s
vendor/llvm/dist/test/tools/llvm-mca/X86/SkylakeServer/resources-x86_64.s
vendor/llvm/dist/test/tools/llvm-mca/X86/Znver1/resources-x86_64.s
vendor/llvm/dist/test/tools/llvm-objcopy/strip-debug.test
vendor/llvm/dist/tools/dsymutil/DwarfLinker.cpp
vendor/llvm/dist/tools/dsymutil/DwarfLinker.h
vendor/llvm/dist/tools/dsymutil/MachOUtils.cpp
vendor/llvm/dist/tools/dsymutil/MachOUtils.h
vendor/llvm/dist/tools/dsymutil/dsymutil.cpp
vendor/llvm/dist/tools/llvm-mca/DispatchStage.cpp
vendor/llvm/dist/tools/llvm-mca/DispatchStage.h
vendor/llvm/dist/tools/llvm-mca/InstrBuilder.cpp
vendor/llvm/dist/tools/llvm-mca/Instruction.h
vendor/llvm/dist/tools/llvm-mca/RetireControlUnit.h
vendor/llvm/dist/tools/llvm-mca/RetireStage.cpp
vendor/llvm/dist/tools/llvm-mca/llvm-mca.cpp
vendor/llvm/dist/tools/llvm-objcopy/llvm-objcopy.cpp
vendor/llvm/dist/tools/llvm-pdbutil/MinimalSymbolDumper.cpp
vendor/llvm/dist/unittests/DebugInfo/CodeView/TypeIndexDiscoveryTest.cpp
vendor/llvm/dist/unittests/DebugInfo/DWARF/DWARFDebugInfoTest.cpp
vendor/llvm/dist/unittests/ExecutionEngine/Orc/RPCUtilsTest.cpp
vendor/llvm/dist/unittests/Transforms/Vectorize/CMakeLists.txt
vendor/llvm/dist/unittests/Transforms/Vectorize/VPlanTestBase.h
vendor/llvm/dist/utils/LLVMVisualizers/llvm.natvis
vendor/llvm/dist/utils/TableGen/CodeGenDAGPatterns.cpp
Modified: vendor/llvm/dist/cmake/modules/AddLLVM.cmake
==============================================================================
--- vendor/llvm/dist/cmake/modules/AddLLVM.cmake Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/cmake/modules/AddLLVM.cmake Thu Aug 2 17:32:43 2018 (r337137)
@@ -867,6 +867,7 @@ if(NOT LLVM_TOOLCHAIN_TOOLS)
llvm-ranlib
llvm-lib
llvm-objdump
+ llvm-rc
)
endif()
Modified: vendor/llvm/dist/docs/CommandGuide/llvm-mca.rst
==============================================================================
--- vendor/llvm/dist/docs/CommandGuide/llvm-mca.rst Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/docs/CommandGuide/llvm-mca.rst Thu Aug 2 17:32:43 2018 (r337137)
@@ -114,8 +114,8 @@ option specifies "``-``", then the output will also be
.. option:: -register-file-size=<size>
Specify the size of the register file. When specified, this flag limits how
- many temporary registers are available for register renaming purposes. A value
- of zero for this flag means "unlimited number of temporary registers".
+ many physical registers are available for register renaming purposes. A value
+ of zero for this flag means "unlimited number of physical registers".
.. option:: -iterations=<number of iterations>
@@ -207,23 +207,23 @@ EXIT STATUS
:program:`llvm-mca` returns 0 on success. Otherwise, an error message is printed
to standard error, and the tool returns 1.
-HOW MCA WORKS
--------------
+HOW LLVM-MCA WORKS
+------------------
-MCA takes assembly code as input. The assembly code is parsed into a sequence
-of MCInst with the help of the existing LLVM target assembly parsers. The
-parsed sequence of MCInst is then analyzed by a ``Pipeline`` module to generate
-a performance report.
+:program:`llvm-mca` takes assembly code as input. The assembly code is parsed
+into a sequence of MCInst with the help of the existing LLVM target assembly
+parsers. The parsed sequence of MCInst is then analyzed by a ``Pipeline`` module
+to generate a performance report.
The Pipeline module simulates the execution of the machine code sequence in a
loop of iterations (default is 100). During this process, the pipeline collects
a number of execution related statistics. At the end of this process, the
pipeline generates and prints a report from the collected statistics.
-Here is an example of a performance report generated by MCA for a dot-product
-of two packed float vectors of four elements. The analysis is conducted for
-target x86, cpu btver2. The following result can be produced via the following
-command using the example located at
+Here is an example of a performance report generated by the tool for a
+dot-product of two packed float vectors of four elements. The analysis is
+conducted for target x86, cpu btver2. The following result can be produced via
+the following command using the example located at
``test/tools/llvm-mca/X86/BtVer2/dot-product.s``:
.. code-block:: bash
@@ -287,11 +287,31 @@ for a total of 900 dynamically executed instructions.
The report is structured in three main sections. The first section collects a
few performance numbers; the goal of this section is to give a very quick
overview of the performance throughput. In this example, the two important
-performance indicators are the predicted total number of cycles, and the IPC.
-IPC is probably the most important throughput indicator. A big delta between
-the Dispatch Width and the computed IPC is an indicator of potential
-performance issues.
+performance indicators are **IPC** and **Block RThroughput** (Block Reciprocal
+Throughput).
+IPC is computed dividing the total number of simulated instructions by the total
+number of cycles. A delta between Dispatch Width and IPC is an indicator of a
+performance issue. In the absence of loop-carried data dependencies, the
+observed IPC tends to a theoretical maximum which can be computed by dividing
+the number of instructions of a single iteration by the *Block RThroughput*.
+
+IPC is bounded from above by the dispatch width. That is because the dispatch
+width limits the maximum size of a dispatch group. IPC is also limited by the
+amount of hardware parallelism. The availability of hardware resources affects
+the resource pressure distribution, and it limits the number of instructions
+that can be executed in parallel every cycle. A delta between Dispatch
+Width and the theoretical maximum IPC is an indicator of a performance
+bottleneck caused by the lack of hardware resources. In general, the lower the
+Block RThroughput, the better.
+
+In this example, ``Instructions per iteration/Block RThroughput`` is 1.50. Since
+there are no loop-carried dependencies, the observed IPC is expected to approach
+1.50 when the number of iterations tends to infinity. The delta between the
+Dispatch Width (2.00), and the theoretical maximum IPC (1.50) is an indicator of
+a performance bottleneck caused by the lack of hardware resources, and the
+*Resource pressure view* can help to identify the problematic resource usage.
+
The second section of the report shows the latency and reciprocal
throughput of every instruction in the sequence. That section also reports
extra information related to the number of micro opcodes, and opcode properties
@@ -316,7 +336,7 @@ pressure should be uniformly distributed between multi
Timeline View
^^^^^^^^^^^^^
-MCA's timeline view produces a detailed report of each instruction's state
+The timeline view produces a detailed report of each instruction's state
transitions through an instruction pipeline. This view is enabled by the
command line option ``-timeline``. As instructions transition through the
various stages of the pipeline, their states are depicted in the view report.
@@ -331,7 +351,7 @@ These states are represented by the following characte
Below is the timeline view for a subset of the dot-product example located in
``test/tools/llvm-mca/X86/BtVer2/dot-product.s`` and processed by
-MCA using the following command:
+:program:`llvm-mca` using the following command:
.. code-block:: bash
@@ -366,7 +386,7 @@ MCA using the following command:
2. 3 5.7 0.0 0.0 vhaddps %xmm3, %xmm3, %xmm4
The timeline view is interesting because it shows instruction state changes
-during execution. It also gives an idea of how MCA processes instructions
+during execution. It also gives an idea of how the tool processes instructions
executed on the target, and how their timing information might be calculated.
The timeline view is structured in two tables. The first table shows
@@ -411,12 +431,12 @@ Parallelism).
In the dot-product example, there are anti-dependencies introduced by
instructions from different iterations. However, those dependencies can be
removed at register renaming stage (at the cost of allocating register aliases,
-and therefore consuming temporary registers).
+and therefore consuming physical registers).
Table *Average Wait times* helps diagnose performance issues that are caused by
the presence of long latency instructions and potentially long data dependencies
-which may limit the ILP. Note that MCA, by default, assumes at least 1cy
-between the dispatch event and the issue event.
+which may limit the ILP. Note that :program:`llvm-mca`, by default, assumes at
+least 1cy between the dispatch event and the issue event.
When the performance is limited by data dependencies and/or long latency
instructions, the number of cycles spent while in the *ready* state is expected
@@ -549,3 +569,177 @@ statistics are displayed by using the command option `
In this example, we can conclude that the IPC is mostly limited by data
dependencies, and not by resource pressure.
+
+Instruction Flow
+^^^^^^^^^^^^^^^^
+This section describes the instruction flow through MCA's default out-of-order
+pipeline, as well as the functional units involved in the process.
+
+The default pipeline implements the following sequence of stages used to
+process instructions.
+
+* Dispatch (Instruction is dispatched to the schedulers).
+* Issue (Instruction is issued to the processor pipelines).
+* Write Back (Instruction is executed, and results are written back).
+* Retire (Instruction is retired; writes are architecturally committed).
+
+The default pipeline only models the out-of-order portion of a processor.
+Therefore, the instruction fetch and decode stages are not modeled. Performance
+bottlenecks in the frontend are not diagnosed. MCA assumes that instructions
+have all been decoded and placed into a queue. Also, MCA does not model branch
+prediction.
+
+Instruction Dispatch
+""""""""""""""""""""
+During the dispatch stage, instructions are picked in program order from a
+queue of already decoded instructions, and dispatched in groups to the
+simulated hardware schedulers.
+
+The size of a dispatch group depends on the availability of the simulated
+hardware resources. The processor dispatch width defaults to the value
+of the ``IssueWidth`` in LLVM's scheduling model.
+
+An instruction can be dispatched if:
+
+* The size of the dispatch group is smaller than processor's dispatch width.
+* There are enough entries in the reorder buffer.
+* There are enough physical registers to do register renaming.
+* The schedulers are not full.
+
+Scheduling models can optionally specify which register files are available on
+the processor. MCA uses that information to initialize register file
+descriptors. Users can limit the number of physical registers that are
+globally available for register renaming by using the command option
+``-register-file-size``. A value of zero for this option means *unbounded*.
+By knowing how many registers are available for renaming, MCA can predict
+dispatch stalls caused by the lack of registers.
+
+The number of reorder buffer entries consumed by an instruction depends on the
+number of micro-opcodes specified by the target scheduling model. MCA's
+reorder buffer's purpose is to track the progress of instructions that are
+"in-flight," and to retire instructions in program order. The number of
+entries in the reorder buffer defaults to the `MicroOpBufferSize` provided by
+the target scheduling model.
+
+Instructions that are dispatched to the schedulers consume scheduler buffer
+entries. :program:`llvm-mca` queries the scheduling model to determine the set
+of buffered resources consumed by an instruction. Buffered resources are
+treated like scheduler resources.
+
+Instruction Issue
+"""""""""""""""""
+Each processor scheduler implements a buffer of instructions. An instruction
+has to wait in the scheduler's buffer until input register operands become
+available. Only at that point, does the instruction becomes eligible for
+execution and may be issued (potentially out-of-order) for execution.
+Instruction latencies are computed by :program:`llvm-mca` with the help of the
+scheduling model.
+
+:program:`llvm-mca`'s scheduler is designed to simulate multiple processor
+schedulers. The scheduler is responsible for tracking data dependencies, and
+dynamically selecting which processor resources are consumed by instructions.
+It delegates the management of processor resource units and resource groups to a
+resource manager. The resource manager is responsible for selecting resource
+units that are consumed by instructions. For example, if an instruction
+consumes 1cy of a resource group, the resource manager selects one of the
+available units from the group; by default, the resource manager uses a
+round-robin selector to guarantee that resource usage is uniformly distributed
+between all units of a group.
+
+:program:`llvm-mca`'s scheduler implements three instruction queues:
+
+* WaitQueue: a queue of instructions whose operands are not ready.
+* ReadyQueue: a queue of instructions ready to execute.
+* IssuedQueue: a queue of instructions executing.
+
+Depending on the operand availability, instructions that are dispatched to the
+scheduler are either placed into the WaitQueue or into the ReadyQueue.
+
+Every cycle, the scheduler checks if instructions can be moved from the
+WaitQueue to the ReadyQueue, and if instructions from the ReadyQueue can be
+issued to the underlying pipelines. The algorithm prioritizes older instructions
+over younger instructions.
+
+Write-Back and Retire Stage
+"""""""""""""""""""""""""""
+Issued instructions are moved from the ReadyQueue to the IssuedQueue. There,
+instructions wait until they reach the write-back stage. At that point, they
+get removed from the queue and the retire control unit is notified.
+
+When instructions are executed, the retire control unit flags the
+instruction as "ready to retire."
+
+Instructions are retired in program order. The register file is notified of
+the retirement so that it can free the physical registers that were allocated
+for the instruction during the register renaming stage.
+
+Load/Store Unit and Memory Consistency Model
+""""""""""""""""""""""""""""""""""""""""""""
+To simulate an out-of-order execution of memory operations, :program:`llvm-mca`
+utilizes a simulated load/store unit (LSUnit) to simulate the speculative
+execution of loads and stores.
+
+Each load (or store) consumes an entry in the load (or store) queue. Users can
+specify flags ``-lqueue`` and ``-squeue`` to limit the number of entries in the
+load and store queues respectively. The queues are unbounded by default.
+
+The LSUnit implements a relaxed consistency model for memory loads and stores.
+The rules are:
+
+1. A younger load is allowed to pass an older load only if there are no
+ intervening stores or barriers between the two loads.
+2. A younger load is allowed to pass an older store provided that the load does
+ not alias with the store.
+3. A younger store is not allowed to pass an older store.
+4. A younger store is not allowed to pass an older load.
+
+By default, the LSUnit optimistically assumes that loads do not alias
+(`-noalias=true`) store operations. Under this assumption, younger loads are
+always allowed to pass older stores. Essentially, the LSUnit does not attempt
+to run any alias analysis to predict when loads and stores do not alias with
+each other.
+
+Note that, in the case of write-combining memory, rule 3 could be relaxed to
+allow reordering of non-aliasing store operations. That being said, at the
+moment, there is no way to further relax the memory model (``-noalias`` is the
+only option). Essentially, there is no option to specify a different memory
+type (e.g., write-back, write-combining, write-through; etc.) and consequently
+to weaken, or strengthen, the memory model.
+
+Other limitations are:
+
+* The LSUnit does not know when store-to-load forwarding may occur.
+* The LSUnit does not know anything about cache hierarchy and memory types.
+* The LSUnit does not know how to identify serializing operations and memory
+ fences.
+
+The LSUnit does not attempt to predict if a load or store hits or misses the L1
+cache. It only knows if an instruction "MayLoad" and/or "MayStore." For
+loads, the scheduling model provides an "optimistic" load-to-use latency (which
+usually matches the load-to-use latency for when there is a hit in the L1D).
+
+:program:`llvm-mca` does not know about serializing operations or memory-barrier
+like instructions. The LSUnit conservatively assumes that an instruction which
+has both "MayLoad" and unmodeled side effects behaves like a "soft"
+load-barrier. That means, it serializes loads without forcing a flush of the
+load queue. Similarly, instructions that "MayStore" and have unmodeled side
+effects are treated like store barriers. A full memory barrier is a "MayLoad"
+and "MayStore" instruction with unmodeled side effects. This is inaccurate, but
+it is the best that we can do at the moment with the current information
+available in LLVM.
+
+A load/store barrier consumes one entry of the load/store queue. A load/store
+barrier enforces ordering of loads/stores. A younger load cannot pass a load
+barrier. Also, a younger store cannot pass a store barrier. A younger load
+has to wait for the memory/load barrier to execute. A load/store barrier is
+"executed" when it becomes the oldest entry in the load/store queue(s). That
+also means, by construction, all of the older loads/stores have been executed.
+
+In conclusion, the full set of load/store consistency rules are:
+
+#. A store may not pass a previous store.
+#. A store may not pass a previous load (regardless of ``-noalias``).
+#. A store has to wait until an older store barrier is fully executed.
+#. A load may pass a previous load.
+#. A load may not pass a previous store unless ``-noalias`` is set.
+#. A load has to wait until an older load barrier is fully executed.
Modified: vendor/llvm/dist/docs/GettingStarted.rst
==============================================================================
--- vendor/llvm/dist/docs/GettingStarted.rst Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/docs/GettingStarted.rst Thu Aug 2 17:32:43 2018 (r337137)
@@ -838,7 +838,7 @@ To configure LLVM, follow these steps:
.. code-block:: console
- % cmake -G "Unix Makefiles" -DCMAKE_INSTALL_PREFIX=prefix=/install/path
+ % cmake -G "Unix Makefiles" -DCMAKE_INSTALL_PREFIX=/install/path
[other options] SRC_ROOT
Compiling the LLVM Suite Source Code
Modified: vendor/llvm/dist/docs/LangRef.rst
==============================================================================
--- vendor/llvm/dist/docs/LangRef.rst Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/docs/LangRef.rst Thu Aug 2 17:32:43 2018 (r337137)
@@ -4588,9 +4588,12 @@ DIExpression
``DIExpression`` nodes represent expressions that are inspired by the DWARF
expression language. They are used in :ref:`debug intrinsics<dbg_intrinsics>`
(such as ``llvm.dbg.declare`` and ``llvm.dbg.value``) to describe how the
-referenced LLVM variable relates to the source language variable.
+referenced LLVM variable relates to the source language variable. Debug
+intrinsics are interpreted left-to-right: start by pushing the value/address
+operand of the intrinsic onto a stack, then repeatedly push and evaluate
+opcodes from the DIExpression until the final variable description is produced.
-The current supported vocabulary is limited:
+The current supported opcode vocabulary is limited:
- ``DW_OP_deref`` dereferences the top of the expression stack.
- ``DW_OP_plus`` pops the last two entries from the expression stack, adds
@@ -4610,12 +4613,30 @@ The current supported vocabulary is limited:
- ``DW_OP_stack_value`` marks a constant value.
DWARF specifies three kinds of simple location descriptions: Register, memory,
-and implicit location descriptions. Register and memory location descriptions
-describe the *location* of a source variable (in the sense that a debugger might
-modify its value), whereas implicit locations describe merely the *value* of a
-source variable. DIExpressions also follow this model: A DIExpression that
-doesn't have a trailing ``DW_OP_stack_value`` will describe an *address* when
-combined with a concrete location.
+and implicit location descriptions. Note that a location description is
+defined over certain ranges of a program, i.e the location of a variable may
+change over the course of the program. Register and memory location
+descriptions describe the *concrete location* of a source variable (in the
+sense that a debugger might modify its value), whereas *implicit locations*
+describe merely the actual *value* of a source variable which might not exist
+in registers or in memory (see ``DW_OP_stack_value``).
+
+A ``llvm.dbg.addr`` or ``llvm.dbg.declare`` intrinsic describes an indirect
+value (the address) of a source variable. The first operand of the intrinsic
+must be an address of some kind. A DIExpression attached to the intrinsic
+refines this address to produce a concrete location for the source variable.
+
+A ``llvm.dbg.value`` intrinsic describes the direct value of a source variable.
+The first operand of the intrinsic may be a direct or indirect value. A
+DIExpresion attached to the intrinsic refines the first operand to produce a
+direct value. For example, if the first operand is an indirect value, it may be
+necessary to insert ``DW_OP_deref`` into the DIExpresion in order to produce a
+valid debug intrinsic.
+
+.. note::
+
+ A DIExpression is interpreted in the same way regardless of which kind of
+ debug intrinsic it's attached to.
.. code-block:: text
Modified: vendor/llvm/dist/docs/SourceLevelDebugging.rst
==============================================================================
--- vendor/llvm/dist/docs/SourceLevelDebugging.rst Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/docs/SourceLevelDebugging.rst Thu Aug 2 17:32:43 2018 (r337137)
@@ -244,6 +244,11 @@ argument is a `local variable <LangRef.html#dilocalvar
description of the variable. The third argument is a `complex expression
<LangRef.html#diexpression>`_.
+An `llvm.dbg.value` intrinsic describes the *value* of a source variable
+directly, not its address. Note that the value operand of this intrinsic may
+be indirect (i.e, a pointer to the source variable), provided that interpreting
+the complex expression derives the direct value.
+
Object lifetimes and scoping
============================
Modified: vendor/llvm/dist/include/llvm/ADT/DenseSet.h
==============================================================================
--- vendor/llvm/dist/include/llvm/ADT/DenseSet.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/ADT/DenseSet.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -17,7 +17,7 @@
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/DenseMapInfo.h"
#include "llvm/Support/type_traits.h"
-#include <algorithm>
+#include <algorithm>
#include <cstddef>
#include <initializer_list>
#include <iterator>
Modified: vendor/llvm/dist/include/llvm/Analysis/BasicAliasAnalysis.h
==============================================================================
--- vendor/llvm/dist/include/llvm/Analysis/BasicAliasAnalysis.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/Analysis/BasicAliasAnalysis.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -43,6 +43,7 @@ class LoopInfo;
class PHINode;
class SelectInst;
class TargetLibraryInfo;
+class PhiValues;
class Value;
/// This is the AA result object for the basic, local, and stateless alias
@@ -60,19 +61,22 @@ class BasicAAResult : public AAResultBase<BasicAAResul
AssumptionCache &AC;
DominatorTree *DT;
LoopInfo *LI;
+ PhiValues *PV;
public:
BasicAAResult(const DataLayout &DL, const Function &F,
const TargetLibraryInfo &TLI, AssumptionCache &AC,
- DominatorTree *DT = nullptr, LoopInfo *LI = nullptr)
- : AAResultBase(), DL(DL), F(F), TLI(TLI), AC(AC), DT(DT), LI(LI) {}
+ DominatorTree *DT = nullptr, LoopInfo *LI = nullptr,
+ PhiValues *PV = nullptr)
+ : AAResultBase(), DL(DL), F(F), TLI(TLI), AC(AC), DT(DT), LI(LI), PV(PV)
+ {}
BasicAAResult(const BasicAAResult &Arg)
: AAResultBase(Arg), DL(Arg.DL), F(Arg.F), TLI(Arg.TLI), AC(Arg.AC),
- DT(Arg.DT), LI(Arg.LI) {}
+ DT(Arg.DT), LI(Arg.LI), PV(Arg.PV) {}
BasicAAResult(BasicAAResult &&Arg)
: AAResultBase(std::move(Arg)), DL(Arg.DL), F(Arg.F), TLI(Arg.TLI),
- AC(Arg.AC), DT(Arg.DT), LI(Arg.LI) {}
+ AC(Arg.AC), DT(Arg.DT), LI(Arg.LI), PV(Arg.PV) {}
/// Handle invalidation events in the new pass manager.
bool invalidate(Function &Fn, const PreservedAnalyses &PA,
Modified: vendor/llvm/dist/include/llvm/Analysis/LoopAccessAnalysis.h
==============================================================================
--- vendor/llvm/dist/include/llvm/Analysis/LoopAccessAnalysis.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/Analysis/LoopAccessAnalysis.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -682,7 +682,7 @@ bool sortPtrAccesses(ArrayRef<Value *> VL, const DataL
SmallVectorImpl<unsigned> &SortedIndices);
/// Returns true if the memory operations \p A and \p B are consecutive.
-/// This is a simple API that does not depend on the analysis pass.
+/// This is a simple API that does not depend on the analysis pass.
bool isConsecutiveAccess(Value *A, Value *B, const DataLayout &DL,
ScalarEvolution &SE, bool CheckType = true);
@@ -734,7 +734,7 @@ class LoopAccessLegacyAnalysis : public FunctionPass {
/// accesses of a loop.
///
/// It runs the analysis for a loop on demand. This can be initiated by
-/// querying the loop access info via AM.getResult<LoopAccessAnalysis>.
+/// querying the loop access info via AM.getResult<LoopAccessAnalysis>.
/// getResult return a LoopAccessInfo object. See this class for the
/// specifics of what information is provided.
class LoopAccessAnalysis
Modified: vendor/llvm/dist/include/llvm/Analysis/MemoryDependenceAnalysis.h
==============================================================================
--- vendor/llvm/dist/include/llvm/Analysis/MemoryDependenceAnalysis.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/Analysis/MemoryDependenceAnalysis.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -44,6 +44,7 @@ class Instruction;
class LoadInst;
class PHITransAddr;
class TargetLibraryInfo;
+class PhiValues;
class Value;
/// A memory dependence query can return one of three different answers.
@@ -360,13 +361,14 @@ class MemoryDependenceResults { (private)
AssumptionCache &AC;
const TargetLibraryInfo &TLI;
DominatorTree &DT;
+ PhiValues &PV;
PredIteratorCache PredCache;
public:
MemoryDependenceResults(AliasAnalysis &AA, AssumptionCache &AC,
const TargetLibraryInfo &TLI,
- DominatorTree &DT)
- : AA(AA), AC(AC), TLI(TLI), DT(DT) {}
+ DominatorTree &DT, PhiValues &PV)
+ : AA(AA), AC(AC), TLI(TLI), DT(DT), PV(PV) {}
/// Handle invalidation in the new PM.
bool invalidate(Function &F, const PreservedAnalyses &PA,
Modified: vendor/llvm/dist/include/llvm/Analysis/MustExecute.h
==============================================================================
--- vendor/llvm/dist/include/llvm/Analysis/MustExecute.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/Analysis/MustExecute.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -10,7 +10,7 @@
/// Contains a collection of routines for determining if a given instruction is
/// guaranteed to execute if a given point in control flow is reached. The most
/// common example is an instruction within a loop being provably executed if we
-/// branch to the header of it's containing loop.
+/// branch to the header of it's containing loop.
///
//===----------------------------------------------------------------------===//
@@ -58,7 +58,7 @@ void computeLoopSafetyInfo(LoopSafetyInfo *, Loop *);
bool isGuaranteedToExecute(const Instruction &Inst, const DominatorTree *DT,
const Loop *CurLoop,
const LoopSafetyInfo *SafetyInfo);
-
+
}
#endif
Modified: vendor/llvm/dist/include/llvm/Analysis/TargetTransformInfoImpl.h
==============================================================================
--- vendor/llvm/dist/include/llvm/Analysis/TargetTransformInfoImpl.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/Analysis/TargetTransformInfoImpl.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -326,7 +326,7 @@ class TargetTransformInfoImplBase { (public)
bool haveFastSqrt(Type *Ty) { return false; }
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) { return true; }
-
+
unsigned getFPOpCost(Type *Ty) { return TargetTransformInfo::TCC_Basic; }
int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
Modified: vendor/llvm/dist/include/llvm/Analysis/ValueTracking.h
==============================================================================
--- vendor/llvm/dist/include/llvm/Analysis/ValueTracking.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/Analysis/ValueTracking.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -464,7 +464,7 @@ class Value;
/// This is equivelent to saying that all instructions within the basic block
/// are guaranteed to transfer execution to their successor within the basic
/// block. This has the same assumptions w.r.t. undefined behavior as the
- /// instruction variant of this function.
+ /// instruction variant of this function.
bool isGuaranteedToTransferExecutionToSuccessor(const BasicBlock *BB);
/// Return true if this function can prove that the instruction I
Modified: vendor/llvm/dist/include/llvm/BinaryFormat/Dwarf.def
==============================================================================
--- vendor/llvm/dist/include/llvm/BinaryFormat/Dwarf.def Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/BinaryFormat/Dwarf.def Thu Aug 2 17:32:43 2018 (r337137)
@@ -856,6 +856,7 @@ HANDLE_DW_UT(0x06, split_type)
// TODO: Add Mach-O and COFF names.
// Official DWARF sections.
HANDLE_DWARF_SECTION(DebugAbbrev, ".debug_abbrev", "debug-abbrev")
+HANDLE_DWARF_SECTION(DebugAddr, ".debug_addr", "debug-addr")
HANDLE_DWARF_SECTION(DebugAranges, ".debug_aranges", "debug-aranges")
HANDLE_DWARF_SECTION(DebugInfo, ".debug_info", "debug-info")
HANDLE_DWARF_SECTION(DebugTypes, ".debug_types", "debug-types")
Modified: vendor/llvm/dist/include/llvm/BinaryFormat/ELF.h
==============================================================================
--- vendor/llvm/dist/include/llvm/BinaryFormat/ELF.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/BinaryFormat/ELF.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -413,8 +413,10 @@ enum {
// ARM Specific e_flags
enum : unsigned {
- EF_ARM_SOFT_FLOAT = 0x00000200U,
- EF_ARM_VFP_FLOAT = 0x00000400U,
+ EF_ARM_SOFT_FLOAT = 0x00000200U, // Legacy pre EABI_VER5
+ EF_ARM_ABI_FLOAT_SOFT = 0x00000200U, // EABI_VER5
+ EF_ARM_VFP_FLOAT = 0x00000400U, // Legacy pre EABI_VER5
+ EF_ARM_ABI_FLOAT_HARD = 0x00000400U, // EABI_VER5
EF_ARM_EABI_UNKNOWN = 0x00000000U,
EF_ARM_EABI_VER1 = 0x01000000U,
EF_ARM_EABI_VER2 = 0x02000000U,
Modified: vendor/llvm/dist/include/llvm/CodeGen/GCStrategy.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/GCStrategy.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/CodeGen/GCStrategy.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -104,12 +104,12 @@ class GCStrategy { (public)
const std::string &getName() const { return Name; }
/// By default, write barriers are replaced with simple store
- /// instructions. If true, you must provide a custom pass to lower
+ /// instructions. If true, you must provide a custom pass to lower
/// calls to \@llvm.gcwrite.
bool customWriteBarrier() const { return CustomWriteBarriers; }
/// By default, read barriers are replaced with simple load
- /// instructions. If true, you must provide a custom pass to lower
+ /// instructions. If true, you must provide a custom pass to lower
/// calls to \@llvm.gcread.
bool customReadBarrier() const { return CustomReadBarriers; }
@@ -146,7 +146,7 @@ class GCStrategy { (public)
}
/// By default, roots are left for the code generator so it can generate a
- /// stack map. If true, you must provide a custom pass to lower
+ /// stack map. If true, you must provide a custom pass to lower
/// calls to \@llvm.gcroot.
bool customRoots() const { return CustomRoots; }
Modified: vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -786,7 +786,7 @@ class LegalizerInfo { (public)
/// setAction ({G_ADD, 0, LLT::scalar(32)}, Legal);
/// setLegalizeScalarToDifferentSizeStrategy(
/// G_ADD, 0, widenToLargerTypesAndNarrowToLargest);
- /// will end up defining getAction({G_ADD, 0, T}) to return the following
+ /// will end up defining getAction({G_ADD, 0, T}) to return the following
/// actions for different scalar types T:
/// LLT::scalar(1)..LLT::scalar(31): {WidenScalar, 0, LLT::scalar(32)}
/// LLT::scalar(32): {Legal, 0, LLT::scalar(32)}
@@ -814,7 +814,7 @@ class LegalizerInfo { (public)
VectorElementSizeChangeStrategies[OpcodeIdx][TypeIdx] = S;
}
- /// A SizeChangeStrategy for the common case where legalization for a
+ /// A SizeChangeStrategy for the common case where legalization for a
/// particular operation consists of only supporting a specific set of type
/// sizes. E.g.
/// setAction ({G_DIV, 0, LLT::scalar(32)}, Legal);
Modified: vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -942,6 +942,16 @@ class MachineIRBuilderBase { (public)
/// \return a MachineInstrBuilder for the newly created instruction.
MachineInstrBuilder buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
unsigned Val, MachineMemOperand &MMO);
+
+ /// Build and insert \p Res = G_BLOCK_ADDR \p BA
+ ///
+ /// G_BLOCK_ADDR computes the address of a basic block.
+ ///
+ /// \pre setBasicBlock or setMI must have been called.
+ /// \pre \p Res must be a generic virtual register of a pointer type.
+ ///
+ /// \return The newly created instruction.
+ MachineInstrBuilder buildBlockAddress(unsigned Res, const BlockAddress *BA);
};
/// A CRTP class that contains methods for building instructions that can
Modified: vendor/llvm/dist/include/llvm/CodeGen/MachORelocation.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/MachORelocation.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/CodeGen/MachORelocation.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -27,15 +27,15 @@ namespace llvm {
uint32_t r_symbolnum; // symbol index if r_extern == 1 else section index
bool r_pcrel; // was relocated pc-relative already
uint8_t r_length; // length = 2 ^ r_length
- bool r_extern; //
+ bool r_extern; //
uint8_t r_type; // if not 0, machine-specific relocation type.
bool r_scattered; // 1 = scattered, 0 = non-scattered
int32_t r_value; // the value the item to be relocated is referring
// to.
- public:
+ public:
uint32_t getPackedFields() const {
if (r_scattered)
- return (1 << 31) | (r_pcrel << 30) | ((r_length & 3) << 28) |
+ return (1 << 31) | (r_pcrel << 30) | ((r_length & 3) << 28) |
((r_type & 15) << 24) | (r_address & 0x00FFFFFF);
else
return (r_symbolnum << 8) | (r_pcrel << 7) | ((r_length & 3) << 5) |
@@ -45,8 +45,8 @@ namespace llvm {
uint32_t getRawAddress() const { return r_address; }
MachORelocation(uint32_t addr, uint32_t index, bool pcrel, uint8_t len,
- bool ext, uint8_t type, bool scattered = false,
- int32_t value = 0) :
+ bool ext, uint8_t type, bool scattered = false,
+ int32_t value = 0) :
r_address(addr), r_symbolnum(index), r_pcrel(pcrel), r_length(len),
r_extern(ext), r_type(type), r_scattered(scattered), r_value(value) {}
};
Modified: vendor/llvm/dist/include/llvm/CodeGen/MachineModuleInfo.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/MachineModuleInfo.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/CodeGen/MachineModuleInfo.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -105,7 +105,7 @@ class MachineModuleInfo : public ImmutablePass {
/// basic block's address of label.
MMIAddrLabelMap *AddrLabelSymbols;
- // TODO: Ideally, what we'd like is to have a switch that allows emitting
+ // TODO: Ideally, what we'd like is to have a switch that allows emitting
// synchronous (precise at call-sites only) CFA into .eh_frame. However,
// even under this switch, we'd like .debug_frame to be precise when using
// -g. At this moment, there's no way to specify that some CFI directives
Modified: vendor/llvm/dist/include/llvm/CodeGen/MachineOutliner.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/MachineOutliner.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/CodeGen/MachineOutliner.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -19,6 +19,7 @@
#include "llvm/CodeGen/LiveRegUnits.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/CodeGen/LivePhysRegs.h"
namespace llvm {
namespace outliner {
@@ -74,6 +75,13 @@ struct Candidate { (public)
/// cost model information.
LiveRegUnits LRU;
+ /// Contains the accumulated register liveness information for the
+ /// instructions in this \p Candidate.
+ ///
+ /// This is optionally used by the target to determine which registers have
+ /// been used across the sequence.
+ LiveRegUnits UsedInSequence;
+
/// Return the number of instructions in this Candidate.
unsigned getLength() const { return Len; }
@@ -137,6 +145,12 @@ struct Candidate { (public)
// outlining candidate.
std::for_each(MBB->rbegin(), (MachineBasicBlock::reverse_iterator)front(),
[this](MachineInstr &MI) { LRU.stepBackward(MI); });
+
+ // Walk over the sequence itself and figure out which registers were used
+ // in the sequence.
+ UsedInSequence.init(TRI);
+ std::for_each(front(), std::next(back()),
+ [this](MachineInstr &MI) { UsedInSequence.accumulate(MI); });
}
};
Modified: vendor/llvm/dist/include/llvm/CodeGen/ScheduleDAG.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/ScheduleDAG.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/CodeGen/ScheduleDAG.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -252,7 +252,7 @@ class TargetRegisterInfo;
MachineInstr *Instr = nullptr; ///< Alternatively, a MachineInstr.
public:
- SUnit *OrigNode = nullptr; ///< If not this, the node from which this node
+ SUnit *OrigNode = nullptr; ///< If not this, the node from which this node
/// was cloned. (SD scheduling only)
const MCSchedClassDesc *SchedClass =
Modified: vendor/llvm/dist/include/llvm/CodeGen/StackMaps.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/StackMaps.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/CodeGen/StackMaps.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -156,7 +156,7 @@ class StatepointOpers {
// TODO:: we should change the STATEPOINT representation so that CC and
// Flags should be part of meta operands, with args and deopt operands, and
// gc operands all prefixed by their length and a type code. This would be
- // much more consistent.
+ // much more consistent.
public:
// These values are aboolute offsets into the operands of the statepoint
// instruction.
Modified: vendor/llvm/dist/include/llvm/CodeGen/TargetLowering.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/TargetLowering.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/CodeGen/TargetLowering.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -718,7 +718,7 @@ class TargetLoweringBase { (public)
/// always broken down into scalars in some contexts. This occurs even if the
/// vector type is legal.
virtual unsigned getVectorTypeBreakdownForCallingConv(
- LLVMContext &Context, EVT VT, EVT &IntermediateVT,
+ LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
unsigned &NumIntermediates, MVT &RegisterVT) const {
return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
RegisterVT);
@@ -1174,7 +1174,7 @@ class TargetLoweringBase { (public)
/// are legal for some operations and not for other operations.
/// For MIPS all vector types must be passed through the integer register set.
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
- EVT VT) const {
+ CallingConv::ID CC, EVT VT) const {
return getRegisterType(Context, VT);
}
@@ -1182,6 +1182,7 @@ class TargetLoweringBase { (public)
/// this occurs when a vector type is used, as vector are passed through the
/// integer register set.
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
+ CallingConv::ID CC,
EVT VT) const {
return getNumRegisters(Context, VT);
}
@@ -3489,10 +3490,10 @@ class TargetLowering : public TargetLoweringBase { (pu
//
SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
bool IsAfterLegalization,
- std::vector<SDNode *> *Created) const;
+ SmallVectorImpl<SDNode *> &Created) const;
SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
bool IsAfterLegalization,
- std::vector<SDNode *> *Created) const;
+ SmallVectorImpl<SDNode *> &Created) const;
/// Targets may override this function to provide custom SDIV lowering for
/// power-of-2 denominators. If the target returns an empty SDValue, LLVM
@@ -3500,7 +3501,7 @@ class TargetLowering : public TargetLoweringBase { (pu
/// operations.
virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
SelectionDAG &DAG,
- std::vector<SDNode *> *Created) const;
+ SmallVectorImpl<SDNode *> &Created) const;
/// Indicate whether this target prefers to combine FDIVs with the same
/// divisor. If the transform should never be done, return zero. If the
@@ -3690,7 +3691,7 @@ class TargetLowering : public TargetLoweringBase { (pu
/// Given an LLVM IR type and return type attributes, compute the return value
/// EVTs and flags, and optionally also the offsets, if the return value is
/// being lowered to memory.
-void GetReturnInfo(Type *ReturnType, AttributeList attr,
+void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr,
SmallVectorImpl<ISD::OutputArg> &Outs,
const TargetLowering &TLI, const DataLayout &DL);
Modified: vendor/llvm/dist/include/llvm/CodeGen/TargetPassConfig.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/TargetPassConfig.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/CodeGen/TargetPassConfig.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -16,7 +16,7 @@
#include "llvm/Pass.h"
#include "llvm/Support/CodeGen.h"
-#include <cassert>
+#include <cassert>
#include <string>
namespace llvm {
Modified: vendor/llvm/dist/include/llvm/CodeGen/TargetRegisterInfo.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/TargetRegisterInfo.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/CodeGen/TargetRegisterInfo.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -456,7 +456,7 @@ class TargetRegisterInfo : public MCRegisterInfo { (pu
/// stack frame offset. The first register is closest to the incoming stack
/// pointer if stack grows down, and vice versa.
/// Notice: This function does not take into account disabled CSRs.
- /// In most cases you will want to use instead the function
+ /// In most cases you will want to use instead the function
/// getCalleeSavedRegs that is implemented in MachineRegisterInfo.
virtual const MCPhysReg*
getCalleeSavedRegs(const MachineFunction *MF) const = 0;
@@ -518,7 +518,7 @@ class TargetRegisterInfo : public MCRegisterInfo { (pu
/// guaranteed to be restored before any uses. This is useful for targets that
/// have call sequences where a GOT register may be updated by the caller
/// prior to a call and is guaranteed to be restored (also by the caller)
- /// after the call.
+ /// after the call.
virtual bool isCallerPreservedPhysReg(unsigned PhysReg,
const MachineFunction &MF) const {
return false;
Modified: vendor/llvm/dist/include/llvm/DebugInfo/CodeView/CodeViewSymbols.def
==============================================================================
--- vendor/llvm/dist/include/llvm/DebugInfo/CodeView/CodeViewSymbols.def Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/DebugInfo/CodeView/CodeViewSymbols.def Thu Aug 2 17:32:43 2018 (r337137)
@@ -143,7 +143,6 @@ CV_SYMBOL(S_MANSLOT , 0x1120)
CV_SYMBOL(S_MANMANYREG , 0x1121)
CV_SYMBOL(S_MANREGREL , 0x1122)
CV_SYMBOL(S_MANMANYREG2 , 0x1123)
-CV_SYMBOL(S_UNAMESPACE , 0x1124)
CV_SYMBOL(S_DATAREF , 0x1126)
CV_SYMBOL(S_ANNOTATIONREF , 0x1128)
CV_SYMBOL(S_TOKENREF , 0x1129)
@@ -255,6 +254,7 @@ SYMBOL_RECORD_ALIAS(S_GMANDATA , 0x111d, ManagedG
SYMBOL_RECORD(S_LTHREAD32 , 0x1112, ThreadLocalDataSym)
SYMBOL_RECORD_ALIAS(S_GTHREAD32 , 0x1113, GlobalTLS, ThreadLocalDataSym)
+SYMBOL_RECORD(S_UNAMESPACE , 0x1124, UsingNamespaceSym)
#undef CV_SYMBOL
#undef SYMBOL_RECORD
Modified: vendor/llvm/dist/include/llvm/DebugInfo/CodeView/SymbolRecord.h
==============================================================================
--- vendor/llvm/dist/include/llvm/DebugInfo/CodeView/SymbolRecord.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/DebugInfo/CodeView/SymbolRecord.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -942,6 +942,19 @@ class ThreadLocalDataSym : public SymbolRecord { (publ
uint32_t RecordOffset;
};
+// S_UNAMESPACE
+class UsingNamespaceSym : public SymbolRecord {
+public:
+ explicit UsingNamespaceSym(SymbolRecordKind Kind) : SymbolRecord(Kind) {}
+ explicit UsingNamespaceSym(uint32_t RecordOffset)
+ : SymbolRecord(SymbolRecordKind::RegRelativeSym),
+ RecordOffset(RecordOffset) {}
+
+ StringRef Name;
+
+ uint32_t RecordOffset;
+};
+
// S_ANNOTATION
using CVSymbol = CVRecord<SymbolKind>;
Modified: vendor/llvm/dist/include/llvm/DebugInfo/DIContext.h
==============================================================================
--- vendor/llvm/dist/include/llvm/DebugInfo/DIContext.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/DebugInfo/DIContext.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -154,6 +154,8 @@ enum DIDumpType : unsigned {
struct DIDumpOptions {
unsigned DumpType = DIDT_All;
unsigned RecurseDepth = -1U;
+ uint16_t Version = 0; // DWARF version to assume when extracting.
+ uint8_t AddrSize = 4; // Address byte size to assume when extracting.
bool ShowAddresses = true;
bool ShowChildren = false;
bool ShowParents = false;
Modified: vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFContext.h
==============================================================================
--- vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFContext.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFContext.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -323,6 +323,10 @@ class DWARFContext : public DIContext { (public)
/// have initialized the relevant target descriptions.
Error loadRegisterInfo(const object::ObjectFile &Obj);
+ /// Get address size from CUs.
+ /// TODO: refactor compile_units() to make this const.
+ uint8_t getCUAddrSize();
+
private:
/// Return the compile unit which contains instruction with provided
/// address.
Modified: vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFDataExtractor.h
==============================================================================
--- vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFDataExtractor.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFDataExtractor.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -51,6 +51,8 @@ class DWARFDataExtractor : public DataExtractor { (pub
/// reflect the absolute address of this pointer.
Optional<uint64_t> getEncodedPointer(uint32_t *Offset, uint8_t Encoding,
uint64_t AbsPosOffset = 0) const;
+
+ size_t size() const { return Section == nullptr ? 0 : Section->Data.size(); }
};
} // end namespace llvm
Added: vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFDebugAddr.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFDebugAddr.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -0,0 +1,98 @@
+//===- DWARFDebugAddr.h -------------------------------------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===------------------------------------------------------------------===//
+
+#ifndef LLVM_DEBUGINFO_DWARFDEBUGADDR_H
+#define LLVM_DEBUGINFO_DWARFDEBUGADDR_H
+
+#include "llvm/BinaryFormat/Dwarf.h"
+#include "llvm/DebugInfo/DIContext.h"
+#include "llvm/DebugInfo/DWARF/DWARFDataExtractor.h"
+#include "llvm/Support/Errc.h"
+#include "llvm/Support/Error.h"
+#include <cstdint>
+#include <map>
+#include <vector>
+
+namespace llvm {
+
+class Error;
+class raw_ostream;
+
+/// A class representing an address table as specified in DWARF v5.
+/// The table consists of a header followed by an array of address values from
+/// .debug_addr section.
+class DWARFDebugAddrTable {
+public:
+ struct Header {
+ /// The total length of the entries for this table, not including the length
+ /// field itself.
+ uint32_t Length = 0;
+ /// The DWARF version number.
+ uint16_t Version = 5;
+ /// The size in bytes of an address on the target architecture. For
+ /// segmented addressing, this is the size of the offset portion of the
+ /// address.
+ uint8_t AddrSize;
+ /// The size in bytes of a segment selector on the target architecture.
+ /// If the target system uses a flat address space, this value is 0.
+ uint8_t SegSize = 0;
+ };
+
+private:
+ dwarf::DwarfFormat Format;
+ uint32_t HeaderOffset;
+ Header HeaderData;
+ uint32_t DataSize = 0;
+ std::vector<uint64_t> Addrs;
+
+public:
+ void clear();
+
+ /// Extract an entire table, including all addresses.
+ Error extract(DWARFDataExtractor Data, uint32_t *OffsetPtr,
+ uint16_t Version, uint8_t AddrSize,
+ std::function<void(Error)> WarnCallback);
+
+ uint32_t getHeaderOffset() const { return HeaderOffset; }
+ uint8_t getAddrSize() const { return HeaderData.AddrSize; }
+ void dump(raw_ostream &OS, DIDumpOptions DumpOpts = {}) const;
+
+ /// Return the address based on a given index.
+ Expected<uint64_t> getAddrEntry(uint32_t Index) const;
+
+ /// Return the size of the table header including the length
+ /// but not including the addresses.
+ uint8_t getHeaderSize() const {
+ switch (Format) {
+ case dwarf::DwarfFormat::DWARF32:
+ return 8; // 4 + 2 + 1 + 1
+ case dwarf::DwarfFormat::DWARF64:
+ return 16; // 12 + 2 + 1 + 1
+ }
+ llvm_unreachable("Invalid DWARF format (expected DWARF32 or DWARF64)");
+ }
+
+ /// Returns the length of this table, including the length field, or 0 if the
+ /// length has not been determined (e.g. because the table has not yet been
+ /// parsed, or there was a problem in parsing).
+ uint32_t getLength() const;
+
+ /// Verify that the given length is valid for this table.
+ bool hasValidLength() const { return getLength() != 0; }
+
+ /// Invalidate Length field to stop further processing.
+ void invalidateLength() { HeaderData.Length = 0; }
+
+ /// Returns the length of the array of addresses.
+ uint32_t getDataSize() const;
+};
+
+} // end namespace llvm
+
+#endif // LLVM_DEBUGINFO_DWARFDEBUGADDR_H
Modified: vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFDie.h
==============================================================================
--- vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFDie.h Thu Aug 2 17:06:03 2018 (r337136)
+++ vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFDie.h Thu Aug 2 17:32:43 2018 (r337137)
@@ -46,7 +46,7 @@ class DWARFDie {
public:
DWARFDie() = default;
- DWARFDie(DWARFUnit *Unit, const DWARFDebugInfoEntry * D) : U(Unit), Die(D) {}
+ DWARFDie(DWARFUnit *Unit, const DWARFDebugInfoEntry *D) : U(Unit), Die(D) {}
bool isValid() const { return U && Die; }
explicit operator bool() const { return isValid(); }
@@ -82,9 +82,7 @@ class DWARFDie {
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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