svn commit: r337098 - in stable/11/sys/dev/mlx5: . mlx5_core mlx5_en mlx5_ib
Hans Petter Selasky
hselasky at FreeBSD.org
Thu Aug 2 08:36:55 UTC 2018
Author: hselasky
Date: Thu Aug 2 08:36:51 2018
New Revision: 337098
URL: https://svnweb.freebsd.org/changeset/base/337098
Log:
MFC r336392:
Implement support for Differentiated Service Code Point, DSCP, in mlx5en(4).
The DSCP feature is controlled using a set of sysctl(8) fields under
the qos sysctl directory entry for mlx5en(4).
For Routable RoCE QPs, the DSCP should be set in the QP's address path.
The DSCP's value is derived from the traffic class.
Linux commit:
ed88451e1f2d400fd6a743d0a481631cf9f97550
Sponsored by: Mellanox Technologies
Modified:
stable/11/sys/dev/mlx5/device.h
stable/11/sys/dev/mlx5/driver.h
stable/11/sys/dev/mlx5/mlx5_core/mlx5_core.h
stable/11/sys/dev/mlx5/mlx5_core/mlx5_fw.c
stable/11/sys/dev/mlx5/mlx5_core/mlx5_port.c
stable/11/sys/dev/mlx5/mlx5_en/en.h
stable/11/sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c
stable/11/sys/dev/mlx5/mlx5_ib/mlx5_ib.h
stable/11/sys/dev/mlx5/mlx5_ib/mlx5_ib_main.c
stable/11/sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c
stable/11/sys/dev/mlx5/mlx5_ifc.h
stable/11/sys/dev/mlx5/port.h
Directory Properties:
stable/11/ (props changed)
Modified: stable/11/sys/dev/mlx5/device.h
==============================================================================
--- stable/11/sys/dev/mlx5/device.h Thu Aug 2 08:35:32 2018 (r337097)
+++ stable/11/sys/dev/mlx5/device.h Thu Aug 2 08:36:51 2018 (r337098)
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
+ * Copyright (c) 2013-2018, Mellanox Technologies, Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -47,11 +47,15 @@
#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
#define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld)
+#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
+#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
+#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
+#define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
@@ -109,6 +113,19 @@ __mlx5_mask(typ, fld))
#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
+#define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
+__mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
+__mlx5_mask16(typ, fld))
+
+#define MLX5_SET16(typ, p, fld, v) do { \
+ u16 _v = v; \
+ BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
+ *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
+ cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
+ (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
+ << __mlx5_16_bit_off(typ, fld))); \
+} while (0)
+
#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
__mlx5_64_off(typ, fld)))
@@ -895,6 +912,14 @@ enum mlx5_cap_type {
MLX5_CAP_NUM
};
+enum mlx5_qcam_reg_groups {
+ MLX5_QCAM_REGS_FIRST_128 = 0x0,
+};
+
+enum mlx5_qcam_feature_groups {
+ MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
+};
+
/* GET Dev Caps macros */
#define MLX5_CAP_GEN(mdev, cap) \
MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
@@ -999,6 +1024,12 @@ enum mlx5_cap_type {
#define MLX5_CAP_QOS_MAX(mdev, cap) \
MLX5_GET(qos_cap,\
mdev->hca_caps_max[MLX5_CAP_QOS], cap)
+
+#define MLX5_CAP_QCAM_REG(mdev, fld) \
+ MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
+
+#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
+ MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
enum {
MLX5_CMD_STAT_OK = 0x0,
Modified: stable/11/sys/dev/mlx5/driver.h
==============================================================================
--- stable/11/sys/dev/mlx5/driver.h Thu Aug 2 08:35:32 2018 (r337097)
+++ stable/11/sys/dev/mlx5/driver.h Thu Aug 2 08:36:51 2018 (r337098)
@@ -119,10 +119,13 @@ enum {
};
enum {
+ MLX5_REG_QPTS = 0x4002,
MLX5_REG_QETCR = 0x4005,
MLX5_REG_QPDP = 0x4007,
MLX5_REG_QTCT = 0x400A,
+ MLX5_REG_QPDPM = 0x4013,
MLX5_REG_QHLL = 0x4016,
+ MLX5_REG_QCAM = 0x4019,
MLX5_REG_DCBX_PARAM = 0x4020,
MLX5_REG_DCBX_APP = 0x4021,
MLX5_REG_PCAP = 0x5001,
@@ -626,6 +629,9 @@ struct mlx5_core_dev {
struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
+ struct {
+ u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
+ } caps;
phys_addr_t iseg_base;
struct mlx5_init_seg __iomem *iseg;
enum mlx5_device_state state;
Modified: stable/11/sys/dev/mlx5/mlx5_core/mlx5_core.h
==============================================================================
--- stable/11/sys/dev/mlx5/mlx5_core/mlx5_core.h Thu Aug 2 08:35:32 2018 (r337097)
+++ stable/11/sys/dev/mlx5/mlx5_core/mlx5_core.h Thu Aug 2 08:36:51 2018 (r337098)
@@ -80,6 +80,8 @@ struct mlx5_core_dev;
int mlx5_query_hca_caps(struct mlx5_core_dev *dev);
int mlx5_query_board_id(struct mlx5_core_dev *dev);
+int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
+ u8 feature_group, u8 access_reg_group);
int mlx5_cmd_init_hca(struct mlx5_core_dev *dev);
int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);
int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev);
Modified: stable/11/sys/dev/mlx5/mlx5_core/mlx5_fw.c
==============================================================================
--- stable/11/sys/dev/mlx5/mlx5_core/mlx5_fw.c Thu Aug 2 08:35:32 2018 (r337097)
+++ stable/11/sys/dev/mlx5/mlx5_core/mlx5_fw.c Thu Aug 2 08:36:51 2018 (r337098)
@@ -110,6 +110,13 @@ static int mlx5_core_query_special_contexts(struct mlx
return err;
}
+static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)
+{
+ return mlx5_query_qcam_reg(dev, dev->caps.qcam,
+ MLX5_QCAM_FEATURE_ENHANCED_FEATURES,
+ MLX5_QCAM_REGS_FIRST_128);
+}
+
int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
{
int err;
@@ -185,6 +192,12 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
if (MLX5_CAP_GEN(dev, qos)) {
err = mlx5_core_get_caps(dev, MLX5_CAP_QOS);
+ if (err)
+ return err;
+ }
+
+ if (MLX5_CAP_GEN(dev, qcam_reg)) {
+ err = mlx5_get_qcam_reg(dev);
if (err)
return err;
}
Modified: stable/11/sys/dev/mlx5/mlx5_core/mlx5_port.c
==============================================================================
--- stable/11/sys/dev/mlx5/mlx5_core/mlx5_port.c Thu Aug 2 08:35:32 2018 (r337097)
+++ stable/11/sys/dev/mlx5/mlx5_core/mlx5_port.c Thu Aug 2 08:36:51 2018 (r337098)
@@ -66,6 +66,19 @@ out:
}
EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
+int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
+ u8 feature_group, u8 access_reg_group)
+{
+ u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {};
+ int sz = MLX5_ST_SZ_BYTES(qcam_reg);
+
+ MLX5_SET(qcam_reg, in, feature_group, feature_group);
+ MLX5_SET(qcam_reg, in, access_reg_group, access_reg_group);
+
+ return mlx5_core_access_reg(mdev, in, sz, qcam, sz, MLX5_REG_QCAM, 0, 0);
+}
+EXPORT_SYMBOL_GPL(mlx5_query_qcam_reg);
+
struct mlx5_reg_pcap {
u8 rsvd0;
u8 port_num;
@@ -966,4 +979,102 @@ int mlx5_query_diagnostic_counters(struct mlx5_core_de
MLX5_SET(query_diagnostic_counters_in, in, sample_index, sample_index);
return mlx5_cmd_exec(mdev, in, sizeof(in), out, out_size);
+}
+
+int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state)
+{
+ u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
+ u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
+ int err;
+
+ MLX5_SET(qpts_reg, in, local_port, 1);
+ MLX5_SET(qpts_reg, in, trust_state, trust_state);
+
+ err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
+ sizeof(out), MLX5_REG_QPTS, 0, 1);
+ return err;
+}
+
+int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state)
+{
+ u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
+ u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
+ int err;
+
+ MLX5_SET(qpts_reg, in, local_port, 1);
+
+ err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
+ sizeof(out), MLX5_REG_QPTS, 0, 0);
+ if (!err)
+ *trust_state = MLX5_GET(qpts_reg, out, trust_state);
+
+ return err;
+}
+
+int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, const u8 *dscp2prio)
+{
+ int sz = MLX5_ST_SZ_BYTES(qpdpm_reg);
+ void *qpdpm_dscp;
+ void *out;
+ void *in;
+ int err;
+ int i;
+
+ in = kzalloc(sz, GFP_KERNEL);
+ out = kzalloc(sz, GFP_KERNEL);
+ if (!in || !out) {
+ err = -ENOMEM;
+ goto out;
+ }
+
+ MLX5_SET(qpdpm_reg, in, local_port, 1);
+ err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
+ if (err)
+ goto out;
+
+ memcpy(in, out, sz);
+ MLX5_SET(qpdpm_reg, in, local_port, 1);
+
+ /* Update the corresponding dscp entry */
+ for (i = 0; i < MLX5_MAX_SUPPORTED_DSCP; i++) {
+ qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, in, dscp[i]);
+ MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, prio, dscp2prio[i]);
+ MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, e, 1);
+ }
+ err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 1);
+out:
+ kfree(in);
+ kfree(out);
+ return err;
+}
+
+int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio)
+{
+ int sz = MLX5_ST_SZ_BYTES(qpdpm_reg);
+ void *qpdpm_dscp;
+ void *out;
+ void *in;
+ int err;
+ int i;
+
+ in = kzalloc(sz, GFP_KERNEL);
+ out = kzalloc(sz, GFP_KERNEL);
+ if (!in || !out) {
+ err = -ENOMEM;
+ goto out;
+ }
+
+ MLX5_SET(qpdpm_reg, in, local_port, 1);
+ err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
+ if (err)
+ goto out;
+
+ for (i = 0; i < MLX5_MAX_SUPPORTED_DSCP; i++) {
+ qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, out, dscp[i]);
+ dscp2prio[i] = MLX5_GET16(qpdpm_dscp_reg, qpdpm_dscp, prio);
+ }
+out:
+ kfree(in);
+ kfree(out);
+ return err;
}
Modified: stable/11/sys/dev/mlx5/mlx5_en/en.h
==============================================================================
--- stable/11/sys/dev/mlx5/mlx5_en/en.h Thu Aug 2 08:35:32 2018 (r337097)
+++ stable/11/sys/dev/mlx5/mlx5_en/en.h Thu Aug 2 08:36:51 2018 (r337098)
@@ -476,6 +476,8 @@ struct mlx5e_params_ethtool {
MLX5E_PARAMS(MLX5E_STATS_VAR)
u64 max_bw_value[IEEE_8021QAZ_MAX_TCS];
u8 prio_tc[IEEE_8021QAZ_MAX_TCS];
+ u8 dscp2prio[MLX5_MAX_SUPPORTED_DSCP];
+ u8 trust_state;
};
/* EEPROM Standards for plug in modules */
Modified: stable/11/sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c
==============================================================================
--- stable/11/sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c Thu Aug 2 08:35:32 2018 (r337097)
+++ stable/11/sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c Thu Aug 2 08:36:51 2018 (r337098)
@@ -121,6 +121,30 @@ done:
}
static int
+mlx5e_get_dscp(struct mlx5e_priv *priv)
+{
+ struct mlx5_core_dev *mdev = priv->mdev;
+ int err;
+
+ if (MLX5_CAP_GEN(mdev, qcam_reg) == 0 ||
+ MLX5_CAP_QCAM_REG(mdev, qpts) == 0 ||
+ MLX5_CAP_QCAM_REG(mdev, qpdpm) == 0)
+ return (EOPNOTSUPP);
+
+ PRIV_LOCK(priv);
+ err = -mlx5_query_dscp2prio(mdev, priv->params_ethtool.dscp2prio);
+ if (err)
+ goto done;
+
+ err = -mlx5_query_trust_state(mdev, &priv->params_ethtool.trust_state);
+ if (err)
+ goto done;
+done:
+ PRIV_UNLOCK(priv);
+ return (err);
+}
+
+static int
mlx5e_tc_maxrate_handler(SYSCTL_HANDLER_ARGS)
{
struct mlx5e_priv *priv = arg1;
@@ -229,6 +253,84 @@ done:
return (err);
}
+static int
+mlx5e_trust_state_handler(SYSCTL_HANDLER_ARGS)
+{
+ struct mlx5e_priv *priv = arg1;
+ struct mlx5_core_dev *mdev = priv->mdev;
+ int err;
+ u8 result;
+
+ PRIV_LOCK(priv);
+ result = priv->params_ethtool.trust_state;
+ err = sysctl_handle_8(oidp, &result, 0, req);
+ if (err || !req->newptr ||
+ result == priv->params_ethtool.trust_state)
+ goto done;
+
+ switch (result) {
+ case MLX5_QPTS_TRUST_PCP:
+ case MLX5_QPTS_TRUST_DSCP:
+ break;
+ case MLX5_QPTS_TRUST_BOTH:
+ if (!MLX5_CAP_QCAM_FEATURE(mdev, qpts_trust_both)) {
+ err = EOPNOTSUPP;
+ goto done;
+ }
+ break;
+ default:
+ err = ERANGE;
+ goto done;
+ }
+
+ err = -mlx5_set_trust_state(mdev, result);
+ if (err)
+ goto done;
+
+ priv->params_ethtool.trust_state = result;
+done:
+ PRIV_UNLOCK(priv);
+ return (err);
+}
+
+static int
+mlx5e_dscp_prio_handler(SYSCTL_HANDLER_ARGS)
+{
+ struct mlx5e_priv *priv = arg1;
+ int prio_index = arg2;
+ struct mlx5_core_dev *mdev = priv->mdev;
+ uint8_t dscp2prio[MLX5_MAX_SUPPORTED_DSCP];
+ uint8_t x;
+ int err;
+
+ PRIV_LOCK(priv);
+ err = SYSCTL_OUT(req, priv->params_ethtool.dscp2prio + prio_index,
+ sizeof(priv->params_ethtool.dscp2prio) / 8);
+ if (err || !req->newptr)
+ goto done;
+
+ memcpy(dscp2prio, priv->params_ethtool.dscp2prio, sizeof(dscp2prio));
+ err = SYSCTL_IN(req, dscp2prio + prio_index, sizeof(dscp2prio) / 8);
+ if (err)
+ goto done;
+ for (x = 0; x != MLX5_MAX_SUPPORTED_DSCP; x++) {
+ if (dscp2prio[x] > 7) {
+ err = ERANGE;
+ goto done;
+ }
+ }
+ err = -mlx5_set_dscp2prio(mdev, dscp2prio);
+ if (err)
+ goto done;
+
+ /* update local array */
+ memcpy(priv->params_ethtool.dscp2prio, dscp2prio,
+ sizeof(priv->params_ethtool.dscp2prio));
+done:
+ PRIV_UNLOCK(priv);
+ return (err);
+}
+
#define MLX5_PARAM_OFFSET(n) \
__offsetof(struct mlx5e_priv, params_ethtool.n)
@@ -1009,5 +1111,21 @@ mlx5e_create_ethtool(struct mlx5e_priv *priv)
OID_AUTO, name, CTLTYPE_U8 | CTLFLAG_RW | CTLFLAG_MPSAFE,
priv, i, mlx5e_prio_to_tc_handler, "CU",
"Set priority to traffic class");
+ }
+
+ /* DSCP support */
+ if (mlx5e_get_dscp(priv) == 0) {
+ for (i = 0; i != MLX5_MAX_SUPPORTED_DSCP; i += 8) {
+ char name[32];
+ snprintf(name, sizeof(name), "dscp_%d_%d_prio", i, i + 7);
+ SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(qos_node),
+ OID_AUTO, name, CTLTYPE_U8 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
+ priv, i, mlx5e_dscp_prio_handler, "CU",
+ "Set DSCP to priority mapping, 0..7");
+ }
+ SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(qos_node),
+ OID_AUTO, "trust_state", CTLTYPE_U8 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
+ priv, 0, mlx5e_trust_state_handler, "CU",
+ "Set trust state, 1:PCP 2:DSCP 3:BOTH");
}
}
Modified: stable/11/sys/dev/mlx5/mlx5_ib/mlx5_ib.h
==============================================================================
--- stable/11/sys/dev/mlx5/mlx5_ib/mlx5_ib.h Thu Aug 2 08:35:32 2018 (r337097)
+++ stable/11/sys/dev/mlx5/mlx5_ib/mlx5_ib.h Thu Aug 2 08:36:51 2018 (r337098)
@@ -944,6 +944,8 @@ int mlx5_ib_set_vf_guid(struct ib_device *device, int
__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
int index);
+int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
+ int index, enum ib_gid_type *gid_type);
/* GSI QP helper functions */
struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd,
Modified: stable/11/sys/dev/mlx5/mlx5_ib/mlx5_ib_main.c
==============================================================================
--- stable/11/sys/dev/mlx5/mlx5_ib/mlx5_ib_main.c Thu Aug 2 08:35:32 2018 (r337097)
+++ stable/11/sys/dev/mlx5/mlx5_ib/mlx5_ib_main.c Thu Aug 2 08:36:51 2018 (r337098)
@@ -380,6 +380,27 @@ __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev
return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
}
+int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
+ int index, enum ib_gid_type *gid_type)
+{
+ struct ib_gid_attr attr;
+ union ib_gid gid;
+ int ret;
+
+ ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
+ if (ret)
+ return ret;
+
+ if (!attr.ndev)
+ return -ENODEV;
+
+ dev_put(attr.ndev);
+
+ *gid_type = attr.gid_type;
+
+ return 0;
+}
+
static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
{
if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
Modified: stable/11/sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c
==============================================================================
--- stable/11/sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c Thu Aug 2 08:35:32 2018 (r337097)
+++ stable/11/sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c Thu Aug 2 08:36:51 2018 (r337098)
@@ -2195,6 +2195,7 @@ static int mlx5_set_path(struct mlx5_ib_dev *dev, stru
{
enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
int err;
+ enum ib_gid_type gid_type;
if (attr_mask & IB_QP_PKEY_INDEX)
path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
@@ -2213,10 +2214,16 @@ static int mlx5_set_path(struct mlx5_ib_dev *dev, stru
if (ll == IB_LINK_LAYER_ETHERNET) {
if (!(ah->ah_flags & IB_AH_GRH))
return -EINVAL;
+ err = mlx5_get_roce_gid_type(dev, port, ah->grh.sgid_index,
+ &gid_type);
+ if (err)
+ return err;
memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
ah->grh.sgid_index);
path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
+ if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
+ path->ecn_dscp = (ah->grh.traffic_class >> 2) & 0x3f;
} else {
path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
path->fl_free_ar |=
Modified: stable/11/sys/dev/mlx5/mlx5_ifc.h
==============================================================================
--- stable/11/sys/dev/mlx5/mlx5_ifc.h Thu Aug 2 08:35:32 2018 (r337097)
+++ stable/11/sys/dev/mlx5/mlx5_ifc.h Thu Aug 2 08:36:51 2018 (r337098)
@@ -962,7 +962,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 cc_modify_allowed[0x1];
u8 start_pad[0x1];
u8 cache_line_128byte[0x1];
- u8 reserved_15[0xb];
+ u8 reserved_at_165[0xa];
+ u8 qcam_reg[0x1];
u8 gid_table_size[0x10];
u8 out_of_seq_cnt[0x1];
@@ -8383,6 +8384,43 @@ struct mlx5_ifc_peir_reg_bits {
u8 error_type[0x8];
};
+struct mlx5_ifc_qcam_access_reg_cap_mask {
+ u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
+ u8 qpdpm[0x1];
+ u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
+ u8 qdpm[0x1];
+ u8 qpts[0x1];
+ u8 qcap[0x1];
+ u8 qcam_access_reg_cap_mask_0[0x1];
+};
+
+struct mlx5_ifc_qcam_qos_feature_cap_mask {
+ u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
+ u8 qpts_trust_both[0x1];
+};
+
+struct mlx5_ifc_qcam_reg_bits {
+ u8 reserved_at_0[0x8];
+ u8 feature_group[0x8];
+ u8 reserved_at_10[0x8];
+ u8 access_reg_group[0x8];
+ u8 reserved_at_20[0x20];
+
+ union {
+ struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
+ u8 reserved_at_0[0x80];
+ } qos_access_reg_cap_mask;
+
+ u8 reserved_at_c0[0x80];
+
+ union {
+ struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
+ u8 reserved_at_0[0x80];
+ } qos_feature_cap_mask;
+
+ u8 reserved_at_1c0[0x80];
+};
+
struct mlx5_ifc_pcap_reg_bits {
u8 reserved_0[0x8];
u8 local_port[0x8];
@@ -9695,5 +9733,24 @@ union mlx5_ifc_uplink_pci_interface_document_bits {
u8 reserved_0[0x20120];
};
+struct mlx5_ifc_qpdpm_dscp_reg_bits {
+ u8 e[0x1];
+ u8 reserved_at_01[0x0b];
+ u8 prio[0x04];
+};
+
+struct mlx5_ifc_qpdpm_reg_bits {
+ u8 reserved_at_0[0x8];
+ u8 local_port[0x8];
+ u8 reserved_at_10[0x10];
+ struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
+};
+
+struct mlx5_ifc_qpts_reg_bits {
+ u8 reserved_at_0[0x8];
+ u8 local_port[0x8];
+ u8 reserved_at_10[0x2d];
+ u8 trust_state[0x3];
+};
#endif /* MLX5_IFC_H */
Modified: stable/11/sys/dev/mlx5/port.h
==============================================================================
--- stable/11/sys/dev/mlx5/port.h Thu Aug 2 08:35:32 2018 (r337097)
+++ stable/11/sys/dev/mlx5/port.h Thu Aug 2 08:36:51 2018 (r337098)
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2016, Mellanox Technologies, Ltd. All rights reserved.
+ * Copyright (c) 2016-2018, Mellanox Technologies, Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -102,6 +102,12 @@ enum mlx5e_connector_type {
MLX5E_CONNECTOR_TYPE_NUMBER,
};
+enum mlx5_qpts_trust_state {
+ MLX5_QPTS_TRUST_PCP = 1,
+ MLX5_QPTS_TRUST_DSCP = 2,
+ MLX5_QPTS_TRUST_BOTH = 3,
+};
+
#define MLX5E_PROT_MASK(link_mode) (1 << (link_mode))
#define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF
@@ -155,4 +161,11 @@ int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev
u8 prio, u8 *tc);
int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, int prio_index,
const u8 prio_tc);
+int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state);
+int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state);
+
+#define MLX5_MAX_SUPPORTED_DSCP 64
+int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, const u8 *dscp2prio);
+int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio);
+
#endif /* __MLX5_PORT_H__ */
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