svn commit: r332503 - in head: contrib/llvm/include/llvm/CodeGen contrib/llvm/lib/CodeGen contrib/llvm/lib/Target/X86 contrib/llvm/lib/Target/X86/Disassembler contrib/llvm/tools/clang/include/clang...
Dimitry Andric
dim at FreeBSD.org
Sat Apr 14 14:57:35 UTC 2018
Author: dim
Date: Sat Apr 14 14:57:32 2018
New Revision: 332503
URL: https://svnweb.freebsd.org/changeset/base/332503
Log:
Revert r332501 for now, as it can cause build failures on i386.
Reported upstream as <https://bugs.llvm.org/show_bug.cgi?id=37133>.
Reported by: emaste, ci.freebsd.org
PR: 225330
Deleted:
head/contrib/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
Modified:
head/contrib/llvm/include/llvm/CodeGen/MachineBasicBlock.h
head/contrib/llvm/lib/CodeGen/MachineBasicBlock.cpp
head/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
head/contrib/llvm/lib/Target/X86/X86.h
head/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp
head/contrib/llvm/lib/Target/X86/X86ISelLowering.h
head/contrib/llvm/lib/Target/X86/X86InstrCompiler.td
head/contrib/llvm/lib/Target/X86/X86InstrInfo.cpp
head/contrib/llvm/lib/Target/X86/X86InstrInfo.h
head/contrib/llvm/lib/Target/X86/X86InstrInfo.td
head/contrib/llvm/lib/Target/X86/X86InstrSystem.td
head/contrib/llvm/lib/Target/X86/X86RegisterInfo.td
head/contrib/llvm/lib/Target/X86/X86Schedule.td
head/contrib/llvm/lib/Target/X86/X86ScheduleAtom.td
head/contrib/llvm/lib/Target/X86/X86TargetMachine.cpp
head/contrib/llvm/tools/clang/include/clang/Driver/Options.td
head/contrib/llvm/tools/clang/lib/Basic/Targets/X86.cpp
head/contrib/llvm/tools/clang/lib/Basic/Targets/X86.h
head/lib/clang/freebsd_cc_version.h
head/lib/clang/libllvm/Makefile
Modified: head/contrib/llvm/include/llvm/CodeGen/MachineBasicBlock.h
==============================================================================
--- head/contrib/llvm/include/llvm/CodeGen/MachineBasicBlock.h Sat Apr 14 12:52:34 2018 (r332502)
+++ head/contrib/llvm/include/llvm/CodeGen/MachineBasicBlock.h Sat Apr 14 14:57:32 2018 (r332503)
@@ -449,13 +449,6 @@ class MachineBasicBlock (public)
/// Replace successor OLD with NEW and update probability info.
void replaceSuccessor(MachineBasicBlock *Old, MachineBasicBlock *New);
- /// Copy a successor (and any probability info) from original block to this
- /// block's. Uses an iterator into the original blocks successors.
- ///
- /// This is useful when doing a partial clone of successors. Afterward, the
- /// probabilities may need to be normalized.
- void copySuccessor(MachineBasicBlock *Orig, succ_iterator I);
-
/// Transfers all the successors from MBB to this machine basic block (i.e.,
/// copies all the successors FromMBB and remove all the successors from
/// FromMBB).
Modified: head/contrib/llvm/lib/CodeGen/MachineBasicBlock.cpp
==============================================================================
--- head/contrib/llvm/lib/CodeGen/MachineBasicBlock.cpp Sat Apr 14 12:52:34 2018 (r332502)
+++ head/contrib/llvm/lib/CodeGen/MachineBasicBlock.cpp Sat Apr 14 14:57:32 2018 (r332503)
@@ -646,14 +646,6 @@ void MachineBasicBlock::replaceSuccessor(MachineBasicB
removeSuccessor(OldI);
}
-void MachineBasicBlock::copySuccessor(MachineBasicBlock *Orig,
- succ_iterator I) {
- if (Orig->Probs.empty())
- addSuccessor(*I, Orig->getSuccProbability(I));
- else
- addSuccessorWithoutProb(*I);
-}
-
void MachineBasicBlock::addPredecessor(MachineBasicBlock *Pred) {
Predecessors.push_back(Pred);
}
Modified: head/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp Sat Apr 14 12:52:34 2018 (r332502)
+++ head/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp Sat Apr 14 14:57:32 2018 (r332503)
@@ -265,10 +265,13 @@ MCDisassembler::DecodeStatus X86GenericDisassembler::g
/// @param reg - The Reg to append.
static void translateRegister(MCInst &mcInst, Reg reg) {
#define ENTRY(x) X86::x,
- static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS};
+ uint8_t llvmRegnums[] = {
+ ALL_REGS
+ 0
+ };
#undef ENTRY
- MCPhysReg llvmRegnum = llvmRegnums[reg];
+ uint8_t llvmRegnum = llvmRegnums[reg];
mcInst.addOperand(MCOperand::createReg(llvmRegnum));
}
Modified: head/contrib/llvm/lib/Target/X86/X86.h
==============================================================================
--- head/contrib/llvm/lib/Target/X86/X86.h Sat Apr 14 12:52:34 2018 (r332502)
+++ head/contrib/llvm/lib/Target/X86/X86.h Sat Apr 14 14:57:32 2018 (r332503)
@@ -66,9 +66,6 @@ FunctionPass *createX86OptimizeLEAs();
/// Return a pass that transforms setcc + movzx pairs into xor + setcc.
FunctionPass *createX86FixupSetCC();
-/// Return a pass that lowers EFLAGS copy pseudo instructions.
-FunctionPass *createX86FlagsCopyLoweringPass();
-
/// Return a pass that expands WinAlloca pseudo-instructions.
FunctionPass *createX86WinAllocaExpander();
Modified: head/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp Sat Apr 14 12:52:34 2018 (r332502)
+++ head/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp Sat Apr 14 14:57:32 2018 (r332503)
@@ -27781,16 +27781,11 @@ X86TargetLowering::EmitInstrWithCustomInserter(Machine
MI.getOpcode() == X86::RDFLAGS32 ? X86::PUSHF32 : X86::PUSHF64;
unsigned Pop = MI.getOpcode() == X86::RDFLAGS32 ? X86::POP32r : X86::POP64r;
MachineInstr *Push = BuildMI(*BB, MI, DL, TII->get(PushF));
- // Permit reads of the EFLAGS and DF registers without them being defined.
+ // Permit reads of the FLAGS register without it being defined.
// This intrinsic exists to read external processor state in flags, such as
// the trap flag, interrupt flag, and direction flag, none of which are
// modeled by the backend.
- assert(Push->getOperand(2).getReg() == X86::EFLAGS &&
- "Unexpected register in operand!");
Push->getOperand(2).setIsUndef();
- assert(Push->getOperand(3).getReg() == X86::DF &&
- "Unexpected register in operand!");
- Push->getOperand(3).setIsUndef();
BuildMI(*BB, MI, DL, TII->get(Pop), MI.getOperand(0).getReg());
MI.eraseFromParent(); // The pseudo is gone now.
@@ -37832,6 +37827,25 @@ bool X86TargetLowering::isTypeDesirableForOp(unsigned
case ISD::XOR:
return false;
}
+}
+
+/// This function checks if any of the users of EFLAGS copies the EFLAGS. We
+/// know that the code that lowers COPY of EFLAGS has to use the stack, and if
+/// we don't adjust the stack we clobber the first frame index.
+/// See X86InstrInfo::copyPhysReg.
+static bool hasCopyImplyingStackAdjustment(const MachineFunction &MF) {
+ const MachineRegisterInfo &MRI = MF.getRegInfo();
+ return any_of(MRI.reg_instructions(X86::EFLAGS),
+ [](const MachineInstr &RI) { return RI.isCopy(); });
+}
+
+void X86TargetLowering::finalizeLowering(MachineFunction &MF) const {
+ if (hasCopyImplyingStackAdjustment(MF)) {
+ MachineFrameInfo &MFI = MF.getFrameInfo();
+ MFI.setHasCopyImplyingStackAdjustment(true);
+ }
+
+ TargetLoweringBase::finalizeLowering(MF);
}
/// This method query the target whether it is beneficial for dag combiner to
Modified: head/contrib/llvm/lib/Target/X86/X86ISelLowering.h
==============================================================================
--- head/contrib/llvm/lib/Target/X86/X86ISelLowering.h Sat Apr 14 12:52:34 2018 (r332502)
+++ head/contrib/llvm/lib/Target/X86/X86ISelLowering.h Sat Apr 14 14:57:32 2018 (r332503)
@@ -1100,6 +1100,8 @@ namespace llvm {
unsigned Factor) const override;
+ void finalizeLowering(MachineFunction &MF) const override;
+
protected:
std::pair<const TargetRegisterClass *, uint8_t>
findRepresentativeClass(const TargetRegisterInfo *TRI,
Modified: head/contrib/llvm/lib/Target/X86/X86InstrCompiler.td
==============================================================================
--- head/contrib/llvm/lib/Target/X86/X86InstrCompiler.td Sat Apr 14 12:52:34 2018 (r332502)
+++ head/contrib/llvm/lib/Target/X86/X86InstrCompiler.td Sat Apr 14 14:57:32 2018 (r332503)
@@ -473,7 +473,7 @@ let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP
ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
- XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF],
+ XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
usesCustomInserter = 1, Uses = [ESP, SSP] in {
def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
"# TLS_addr32",
@@ -493,7 +493,7 @@ let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
- XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF],
+ XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
usesCustomInserter = 1, Uses = [RSP, SSP] in {
def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
"# TLS_addr64",
@@ -509,7 +509,7 @@ def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem
// For i386, the address of the thunk is passed on the stack, on return the
// address of the variable is in %eax. %ecx is trashed during the function
// call. All other registers are preserved.
-let Defs = [EAX, ECX, EFLAGS, DF],
+let Defs = [EAX, ECX, EFLAGS],
Uses = [ESP, SSP],
usesCustomInserter = 1 in
def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
@@ -522,7 +522,7 @@ def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym
// %rdi. The lowering will do the right thing with RDI.
// On return the address of the variable is in %rax. All other
// registers are preserved.
-let Defs = [RAX, EFLAGS, DF],
+let Defs = [RAX, EFLAGS],
Uses = [RSP, SSP],
usesCustomInserter = 1 in
def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
Modified: head/contrib/llvm/lib/Target/X86/X86InstrInfo.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/X86/X86InstrInfo.cpp Sat Apr 14 12:52:34 2018 (r332502)
+++ head/contrib/llvm/lib/Target/X86/X86InstrInfo.cpp Sat Apr 14 14:57:32 2018 (r332503)
@@ -5782,7 +5782,7 @@ bool X86InstrInfo::findCommutedOpIndices(MachineInstr
return false;
}
-X86::CondCode X86::getCondFromBranchOpc(unsigned BrOpc) {
+static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
switch (BrOpc) {
default: return X86::COND_INVALID;
case X86::JE_1: return X86::COND_E;
@@ -5805,7 +5805,7 @@ X86::CondCode X86::getCondFromBranchOpc(unsigned BrOpc
}
/// Return condition code of a SET opcode.
-X86::CondCode X86::getCondFromSETOpc(unsigned Opc) {
+static X86::CondCode getCondFromSETOpc(unsigned Opc) {
switch (Opc) {
default: return X86::COND_INVALID;
case X86::SETAr: case X86::SETAm: return X86::COND_A;
@@ -6130,7 +6130,7 @@ void X86InstrInfo::replaceBranchWithTailCall(
if (!I->isBranch())
assert(0 && "Can't find the branch to replace!");
- X86::CondCode CC = X86::getCondFromBranchOpc(I->getOpcode());
+ X86::CondCode CC = getCondFromBranchOpc(I->getOpcode());
assert(BranchCond.size() == 1);
if (CC != BranchCond[0].getImm())
continue;
@@ -6237,7 +6237,7 @@ bool X86InstrInfo::AnalyzeBranchImpl(
}
// Handle conditional branches.
- X86::CondCode BranchCode = X86::getCondFromBranchOpc(I->getOpcode());
+ X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
if (BranchCode == X86::COND_INVALID)
return true; // Can't handle indirect branch.
@@ -6433,7 +6433,7 @@ unsigned X86InstrInfo::removeBranch(MachineBasicBlock
if (I->isDebugValue())
continue;
if (I->getOpcode() != X86::JMP_1 &&
- X86::getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
+ getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
break;
// Remove the branch.
I->eraseFromParent();
@@ -6710,12 +6710,102 @@ void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
return;
}
- if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
- // FIXME: We use a fatal error here because historically LLVM has tried
- // lower some of these physreg copies and we want to ensure we get
- // reasonable bug reports if someone encounters a case no other testing
- // found. This path should be removed after the LLVM 7 release.
- report_fatal_error("Unable to copy EFLAGS physical register!");
+ bool FromEFLAGS = SrcReg == X86::EFLAGS;
+ bool ToEFLAGS = DestReg == X86::EFLAGS;
+ int Reg = FromEFLAGS ? DestReg : SrcReg;
+ bool is32 = X86::GR32RegClass.contains(Reg);
+ bool is64 = X86::GR64RegClass.contains(Reg);
+
+ if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
+ int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
+ int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
+ int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
+ int Pop = is64 ? X86::POP64r : X86::POP32r;
+ int PopF = is64 ? X86::POPF64 : X86::POPF32;
+ int AX = is64 ? X86::RAX : X86::EAX;
+
+ if (!Subtarget.hasLAHFSAHF()) {
+ assert(Subtarget.is64Bit() &&
+ "Not having LAHF/SAHF only happens on 64-bit.");
+ // Moving EFLAGS to / from another register requires a push and a pop.
+ // Notice that we have to adjust the stack if we don't want to clobber the
+ // first frame index. See X86FrameLowering.cpp - usesTheStack.
+ if (FromEFLAGS) {
+ BuildMI(MBB, MI, DL, get(PushF));
+ BuildMI(MBB, MI, DL, get(Pop), DestReg);
+ }
+ if (ToEFLAGS) {
+ BuildMI(MBB, MI, DL, get(Push))
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ BuildMI(MBB, MI, DL, get(PopF));
+ }
+ return;
+ }
+
+ // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
+ // inefficient. Instead:
+ // - Save the overflow flag OF into AL using SETO, and restore it using a
+ // signed 8-bit addition of AL and INT8_MAX.
+ // - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
+ // using LAHF/SAHF.
+ // - When RAX/EAX is live and isn't the destination register, make sure it
+ // isn't clobbered by PUSH/POP'ing it before and after saving/restoring
+ // the flags.
+ // This approach is ~2.25x faster than using PUSHF/POPF.
+ //
+ // This is still somewhat inefficient because we don't know which flags are
+ // actually live inside EFLAGS. Were we able to do a single SETcc instead of
+ // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
+ //
+ // PUSHF/POPF is also potentially incorrect because it affects other flags
+ // such as TF/IF/DF, which LLVM doesn't model.
+ //
+ // Notice that we have to adjust the stack if we don't want to clobber the
+ // first frame index.
+ // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
+
+ const TargetRegisterInfo &TRI = getRegisterInfo();
+ MachineBasicBlock::LivenessQueryResult LQR =
+ MBB.computeRegisterLiveness(&TRI, AX, MI);
+ // We do not want to save and restore AX if we do not have to.
+ // Moreover, if we do so whereas AX is dead, we would need to set
+ // an undef flag on the use of AX, otherwise the verifier will
+ // complain that we read an undef value.
+ // We do not want to change the behavior of the machine verifier
+ // as this is usually wrong to read an undef value.
+ if (MachineBasicBlock::LQR_Unknown == LQR) {
+ LivePhysRegs LPR(TRI);
+ LPR.addLiveOuts(MBB);
+ MachineBasicBlock::iterator I = MBB.end();
+ while (I != MI) {
+ --I;
+ LPR.stepBackward(*I);
+ }
+ // AX contains the top most register in the aliasing hierarchy.
+ // It may not be live, but one of its aliases may be.
+ for (MCRegAliasIterator AI(AX, &TRI, true);
+ AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI)
+ LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live
+ : MachineBasicBlock::LQR_Dead;
+ }
+ bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
+ if (!AXDead)
+ BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
+ if (FromEFLAGS) {
+ BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
+ BuildMI(MBB, MI, DL, get(X86::LAHF));
+ BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
+ }
+ if (ToEFLAGS) {
+ BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
+ BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
+ .addReg(X86::AL)
+ .addImm(INT8_MAX);
+ BuildMI(MBB, MI, DL, get(X86::SAHF));
+ }
+ if (!AXDead)
+ BuildMI(MBB, MI, DL, get(Pop), AX);
+ return;
}
DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
@@ -7375,9 +7465,9 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &
if (IsCmpZero || IsSwapped) {
// We decode the condition code from opcode.
if (Instr.isBranch())
- OldCC = X86::getCondFromBranchOpc(Instr.getOpcode());
+ OldCC = getCondFromBranchOpc(Instr.getOpcode());
else {
- OldCC = X86::getCondFromSETOpc(Instr.getOpcode());
+ OldCC = getCondFromSETOpc(Instr.getOpcode());
if (OldCC != X86::COND_INVALID)
OpcIsSET = true;
else
@@ -9323,9 +9413,8 @@ bool X86InstrInfo::
isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
// FIXME: Return false for x87 stack register classes for now. We can't
// allow any loads of these registers before FpGet_ST0_80.
- return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
- RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
- RC == &X86::RFP80RegClass);
+ return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
+ RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
}
/// Return a virtual register initialized with the
Modified: head/contrib/llvm/lib/Target/X86/X86InstrInfo.h
==============================================================================
--- head/contrib/llvm/lib/Target/X86/X86InstrInfo.h Sat Apr 14 12:52:34 2018 (r332502)
+++ head/contrib/llvm/lib/Target/X86/X86InstrInfo.h Sat Apr 14 14:57:32 2018 (r332503)
@@ -77,12 +77,6 @@ unsigned getSETFromCond(CondCode CC, bool HasMemoryOpe
unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
bool HasMemoryOperand = false);
-// Turn jCC opcode into condition code.
-CondCode getCondFromBranchOpc(unsigned Opc);
-
-// Turn setCC opcode into condition code.
-CondCode getCondFromSETOpc(unsigned Opc);
-
// Turn CMov opcode into condition code.
CondCode getCondFromCMovOpc(unsigned Opc);
Modified: head/contrib/llvm/lib/Target/X86/X86InstrInfo.td
==============================================================================
--- head/contrib/llvm/lib/Target/X86/X86InstrInfo.td Sat Apr 14 12:52:34 2018 (r332502)
+++ head/contrib/llvm/lib/Target/X86/X86InstrInfo.td Sat Apr 14 14:57:32 2018 (r332503)
@@ -1235,18 +1235,18 @@ let mayLoad = 1, mayStore = 1, usesCustomInserter = 1,
let mayLoad = 1, mayStore = 1, usesCustomInserter = 1,
SchedRW = [WriteRMW] in {
- let Defs = [ESP, EFLAGS, DF], Uses = [ESP] in
+ let Defs = [ESP, EFLAGS], Uses = [ESP] in
def WRFLAGS32 : PseudoI<(outs), (ins GR32:$src),
[(int_x86_flags_write_u32 GR32:$src)]>,
Requires<[Not64BitMode]>;
- let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in
+ let Defs = [RSP, EFLAGS], Uses = [RSP] in
def WRFLAGS64 : PseudoI<(outs), (ins GR64:$src),
[(int_x86_flags_write_u64 GR64:$src)]>,
Requires<[In64BitMode]>;
}
-let Defs = [ESP, EFLAGS, DF], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
+let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
SchedRW = [WriteLoad] in {
def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>,
OpSize16;
@@ -1254,7 +1254,7 @@ def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|
OpSize32, Requires<[Not64BitMode]>;
}
-let Defs = [ESP], Uses = [ESP, EFLAGS, DF], mayStore = 1, hasSideEffects=0,
+let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0,
SchedRW = [WriteStore] in {
def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
OpSize16;
@@ -1294,10 +1294,10 @@ def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i
Requires<[In64BitMode]>;
}
-let Defs = [RSP, EFLAGS, DF], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
+let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;
-let Defs = [RSP], Uses = [RSP, EFLAGS, DF], mayStore = 1, hasSideEffects=0 in
+let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
@@ -1382,7 +1382,8 @@ def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (
} // Defs = [EFLAGS]
let SchedRW = [WriteMicrocoded] in {
-let Defs = [EDI,ESI], Uses = [EDI,ESI,DF] in {
+// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
+let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
def MOVSB : I<0xA4, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
"movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
def MOVSW : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
@@ -1393,33 +1394,36 @@ def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs), (ins dstidx
"movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
}
-let Defs = [EDI], Uses = [AL,EDI,DF] in
+// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
+let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
def STOSB : I<0xAA, RawFrmDst, (outs), (ins dstidx8:$dst),
"stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
-let Defs = [EDI], Uses = [AX,EDI,DF] in
+let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
def STOSW : I<0xAB, RawFrmDst, (outs), (ins dstidx16:$dst),
"stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16;
-let Defs = [EDI], Uses = [EAX,EDI,DF] in
+let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
def STOSL : I<0xAB, RawFrmDst, (outs), (ins dstidx32:$dst),
"stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32;
-let Defs = [RDI], Uses = [RAX,RDI,DF] in
+let Defs = [RDI], Uses = [RAX,RDI,EFLAGS] in
def STOSQ : RI<0xAB, RawFrmDst, (outs), (ins dstidx64:$dst),
"stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
-let Defs = [EDI,EFLAGS], Uses = [AL,EDI,DF] in
+// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
+let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in
def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
"scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
-let Defs = [EDI,EFLAGS], Uses = [AX,EDI,DF] in
+let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in
def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
"scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16;
-let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,DF] in
+let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in
def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
"scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32;
-let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,DF] in
+let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in
def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
"scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
-let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,DF] in {
+// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
+let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in {
def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
"cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
@@ -2066,7 +2070,8 @@ def DATA32_PREFIX : I<0x66, RawFrm, (outs), (ins), "d
} // SchedRW
// Repeat string operation instruction prefixes
-let Defs = [ECX], Uses = [ECX,DF], SchedRW = [WriteMicrocoded] in {
+// These use the DF flag in the EFLAGS register to inc or dec ECX
+let Defs = [ECX], Uses = [ECX,EFLAGS], SchedRW = [WriteMicrocoded] in {
// Repeat (used with INS, OUTS, MOVS, LODS and STOS)
def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
// Repeat while not equal (used with CMPS and SCAS)
@@ -2075,22 +2080,24 @@ def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "re
// String manipulation instructions
let SchedRW = [WriteMicrocoded] in {
-let Defs = [AL,ESI], Uses = [ESI,DF] in
+// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
+let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in
def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
"lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
-let Defs = [AX,ESI], Uses = [ESI,DF] in
+let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in
def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
"lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16;
-let Defs = [EAX,ESI], Uses = [ESI,DF] in
+let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in
def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
"lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32;
-let Defs = [RAX,ESI], Uses = [ESI,DF] in
+let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in
def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
"lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
}
let SchedRW = [WriteSystem] in {
-let Defs = [ESI], Uses = [DX,ESI,DF] in {
+// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
+let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in {
def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
"outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
@@ -2099,7 +2106,8 @@ def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$
"outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32;
}
-let Defs = [EDI], Uses = [DX,EDI,DF] in {
+// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
+let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in {
def INSB : I<0x6C, RawFrmDst, (outs), (ins dstidx8:$dst),
"insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
def INSW : I<0x6D, RawFrmDst, (outs), (ins dstidx16:$dst),
@@ -2109,21 +2117,18 @@ def INSL : I<0x6D, RawFrmDst, (outs), (ins dstidx32:$d
}
}
-// EFLAGS management instructions.
-let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in {
-def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC_CMC_STC>;
-def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_CLC_CMC_STC>;
-def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CLC_CMC_STC>;
-}
-
-// DF management instructions.
-// FIXME: These are a bit more expensive than CLC and STC. We should consider
-// adjusting their schedule bucket.
-let SchedRW = [WriteALU], Defs = [DF] in {
+// Flag instructions
+let SchedRW = [WriteALU] in {
+def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
+def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
+def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
+def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
-}
+def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
+def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
+}
// Table lookup instructions
let Uses = [AL,EBX], Defs = [AL], hasSideEffects = 0, mayLoad = 1 in
Modified: head/contrib/llvm/lib/Target/X86/X86InstrSystem.td
==============================================================================
--- head/contrib/llvm/lib/Target/X86/X86InstrSystem.td Sat Apr 14 12:52:34 2018 (r332502)
+++ head/contrib/llvm/lib/Target/X86/X86InstrSystem.td Sat Apr 14 14:57:32 2018 (r332503)
@@ -693,19 +693,6 @@ let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX
} // SchedRW
//===----------------------------------------------------------------------===//
-// TS flag control instruction.
-let SchedRW = [WriteSystem] in {
-def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
-}
-
-//===----------------------------------------------------------------------===//
-// IF (inside EFLAGS) management instructions.
-let SchedRW = [WriteSystem], Uses = [EFLAGS], Defs = [EFLAGS] in {
-def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
-def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
-}
-
-//===----------------------------------------------------------------------===//
// RDPID Instruction
let SchedRW = [WriteSystem] in {
def RDPID32 : I<0xC7, MRM7r, (outs GR32:$src), (ins),
Modified: head/contrib/llvm/lib/Target/X86/X86RegisterInfo.td
==============================================================================
--- head/contrib/llvm/lib/Target/X86/X86RegisterInfo.td Sat Apr 14 12:52:34 2018 (r332502)
+++ head/contrib/llvm/lib/Target/X86/X86RegisterInfo.td Sat Apr 14 14:57:32 2018 (r332503)
@@ -251,19 +251,9 @@ def ST7 : X86Reg<"st(7)", 7>, DwarfRegNum<[40, 19, 18]
// Floating-point status word
def FPSW : X86Reg<"fpsw", 0>;
-// Status flags register.
-//
-// Note that some flags that are commonly thought of as part of the status
-// flags register are modeled separately. Typically this is due to instructions
-// reading and updating those flags independently of all the others. We don't
-// want to create false dependencies between these instructions and so we use
-// a separate register to model them.
+// Status flags register
def EFLAGS : X86Reg<"flags", 0>;
-// The direction flag.
-def DF : X86Reg<"DF", 0>;
-
-
// Segment registers
def CS : X86Reg<"cs", 1>;
def DS : X86Reg<"ds", 3>;
@@ -504,10 +494,6 @@ def CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)
let isAllocatable = 0;
}
def FPCCR : RegisterClass<"X86", [i16], 16, (add FPSW)> {
- let CopyCost = -1; // Don't allow copying of status registers.
- let isAllocatable = 0;
-}
-def DFCCR : RegisterClass<"X86", [i32], 32, (add DF)> {
let CopyCost = -1; // Don't allow copying of status registers.
let isAllocatable = 0;
}
Modified: head/contrib/llvm/lib/Target/X86/X86Schedule.td
==============================================================================
--- head/contrib/llvm/lib/Target/X86/X86Schedule.td Sat Apr 14 12:52:34 2018 (r332502)
+++ head/contrib/llvm/lib/Target/X86/X86Schedule.td Sat Apr 14 14:57:32 2018 (r332503)
@@ -608,10 +608,12 @@ def IIC_CMPXCHG_8B : InstrItinClass;
def IIC_CMPXCHG_16B : InstrItinClass;
def IIC_LODS : InstrItinClass;
def IIC_OUTS : InstrItinClass;
-def IIC_CLC_CMC_STC : InstrItinClass;
+def IIC_CLC : InstrItinClass;
def IIC_CLD : InstrItinClass;
def IIC_CLI : InstrItinClass;
+def IIC_CMC : InstrItinClass;
def IIC_CLTS : InstrItinClass;
+def IIC_STC : InstrItinClass;
def IIC_STI : InstrItinClass;
def IIC_STD : InstrItinClass;
def IIC_XLAT : InstrItinClass;
Modified: head/contrib/llvm/lib/Target/X86/X86ScheduleAtom.td
==============================================================================
--- head/contrib/llvm/lib/Target/X86/X86ScheduleAtom.td Sat Apr 14 12:52:34 2018 (r332502)
+++ head/contrib/llvm/lib/Target/X86/X86ScheduleAtom.td Sat Apr 14 14:57:32 2018 (r332503)
@@ -514,10 +514,12 @@ def AtomItineraries : ProcessorItineraries<
InstrItinData<IIC_CMPXCHG_16B, [InstrStage<22, [Port0, Port1]>] >,
InstrItinData<IIC_LODS, [InstrStage<2, [Port0, Port1]>] >,
InstrItinData<IIC_OUTS, [InstrStage<74, [Port0, Port1]>] >,
- InstrItinData<IIC_CLC_CMC_STC, [InstrStage<1, [Port0, Port1]>] >,
+ InstrItinData<IIC_CLC, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_CLD, [InstrStage<3, [Port0, Port1]>] >,
InstrItinData<IIC_CLI, [InstrStage<14, [Port0, Port1]>] >,
+ InstrItinData<IIC_CMC, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_CLTS, [InstrStage<33, [Port0, Port1]>] >,
+ InstrItinData<IIC_STC, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_STI, [InstrStage<17, [Port0, Port1]>] >,
InstrItinData<IIC_STD, [InstrStage<21, [Port0, Port1]>] >,
InstrItinData<IIC_XLAT, [InstrStage<6, [Port0, Port1]>] >,
Modified: head/contrib/llvm/lib/Target/X86/X86TargetMachine.cpp
==============================================================================
--- head/contrib/llvm/lib/Target/X86/X86TargetMachine.cpp Sat Apr 14 12:52:34 2018 (r332502)
+++ head/contrib/llvm/lib/Target/X86/X86TargetMachine.cpp Sat Apr 14 14:57:32 2018 (r332503)
@@ -62,7 +62,6 @@ void initializeX86CallFrameOptimizationPass(PassRegist
void initializeX86CmovConverterPassPass(PassRegistry &);
void initializeX86ExecutionDepsFixPass(PassRegistry &);
void initializeX86DomainReassignmentPass(PassRegistry &);
-void initializeX86FlagsCopyLoweringPassPass(PassRegistry &);
} // end namespace llvm
@@ -81,7 +80,6 @@ extern "C" void LLVMInitializeX86Target() {
initializeX86CmovConverterPassPass(PR);
initializeX86ExecutionDepsFixPass(PR);
initializeX86DomainReassignmentPass(PR);
- initializeX86FlagsCopyLoweringPassPass(PR);
}
static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
@@ -417,7 +415,6 @@ void X86PassConfig::addPreRegAlloc() {
addPass(createX86CallFrameOptimization());
}
- addPass(createX86FlagsCopyLoweringPass());
addPass(createX86WinAllocaExpander());
}
void X86PassConfig::addMachineSSAOptimization() {
Modified: head/contrib/llvm/tools/clang/include/clang/Driver/Options.td
==============================================================================
--- head/contrib/llvm/tools/clang/include/clang/Driver/Options.td Sat Apr 14 12:52:34 2018 (r332502)
+++ head/contrib/llvm/tools/clang/include/clang/Driver/Options.td Sat Apr 14 14:57:32 2018 (r332503)
@@ -2559,8 +2559,6 @@ def mrtm : Flag<["-"], "mrtm">, Group<m_x86_Features_G
def mno_rtm : Flag<["-"], "mno-rtm">, Group<m_x86_Features_Group>;
def mrdseed : Flag<["-"], "mrdseed">, Group<m_x86_Features_Group>;
def mno_rdseed : Flag<["-"], "mno-rdseed">, Group<m_x86_Features_Group>;
-def msahf : Flag<["-"], "msahf">, Group<m_x86_Features_Group>;
-def mno_sahf : Flag<["-"], "mno-sahf">, Group<m_x86_Features_Group>;
def msgx : Flag<["-"], "msgx">, Group<m_x86_Features_Group>;
def mno_sgx : Flag<["-"], "mno-sgx">, Group<m_x86_Features_Group>;
def msha : Flag<["-"], "msha">, Group<m_x86_Features_Group>;
Modified: head/contrib/llvm/tools/clang/lib/Basic/Targets/X86.cpp
==============================================================================
--- head/contrib/llvm/tools/clang/lib/Basic/Targets/X86.cpp Sat Apr 14 12:52:34 2018 (r332502)
+++ head/contrib/llvm/tools/clang/lib/Basic/Targets/X86.cpp Sat Apr 14 14:57:32 2018 (r332503)
@@ -198,7 +198,6 @@ bool X86TargetInfo::initFeatureMap(
LLVM_FALLTHROUGH;
case CK_Core2:
setFeatureEnabledImpl(Features, "ssse3", true);
- setFeatureEnabledImpl(Features, "sahf", true);
LLVM_FALLTHROUGH;
case CK_Yonah:
case CK_Prescott:
@@ -240,7 +239,6 @@ bool X86TargetInfo::initFeatureMap(
setFeatureEnabledImpl(Features, "ssse3", true);
setFeatureEnabledImpl(Features, "fxsr", true);
setFeatureEnabledImpl(Features, "cx16", true);
- setFeatureEnabledImpl(Features, "sahf", true);
break;
case CK_KNM:
@@ -271,7 +269,6 @@ bool X86TargetInfo::initFeatureMap(
setFeatureEnabledImpl(Features, "xsaveopt", true);
setFeatureEnabledImpl(Features, "xsave", true);
setFeatureEnabledImpl(Features, "movbe", true);
- setFeatureEnabledImpl(Features, "sahf", true);
break;
case CK_K6_2:
@@ -285,7 +282,6 @@ bool X86TargetInfo::initFeatureMap(
setFeatureEnabledImpl(Features, "sse4a", true);
setFeatureEnabledImpl(Features, "lzcnt", true);
setFeatureEnabledImpl(Features, "popcnt", true);
- setFeatureEnabledImpl(Features, "sahf", true);
LLVM_FALLTHROUGH;
case CK_K8SSE3:
setFeatureEnabledImpl(Features, "sse3", true);
@@ -319,7 +315,6 @@ bool X86TargetInfo::initFeatureMap(
setFeatureEnabledImpl(Features, "prfchw", true);
setFeatureEnabledImpl(Features, "cx16", true);
setFeatureEnabledImpl(Features, "fxsr", true);
- setFeatureEnabledImpl(Features, "sahf", true);
break;
case CK_ZNVER1:
@@ -343,7 +338,6 @@ bool X86TargetInfo::initFeatureMap(
setFeatureEnabledImpl(Features, "prfchw", true);
setFeatureEnabledImpl(Features, "rdrnd", true);
setFeatureEnabledImpl(Features, "rdseed", true);
- setFeatureEnabledImpl(Features, "sahf", true);
setFeatureEnabledImpl(Features, "sha", true);
setFeatureEnabledImpl(Features, "sse4a", true);
setFeatureEnabledImpl(Features, "xsave", true);
@@ -378,7 +372,6 @@ bool X86TargetInfo::initFeatureMap(
setFeatureEnabledImpl(Features, "cx16", true);
setFeatureEnabledImpl(Features, "fxsr", true);
setFeatureEnabledImpl(Features, "xsave", true);
- setFeatureEnabledImpl(Features, "sahf", true);
break;
}
if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
@@ -775,8 +768,6 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<s
HasRetpoline = true;
} else if (Feature == "+retpoline-external-thunk") {
HasRetpolineExternalThunk = true;
- } else if (Feature == "+sahf") {
- HasLAHFSAHF = true;
}
X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
@@ -1249,7 +1240,6 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name)
.Case("rdrnd", true)
.Case("rdseed", true)
.Case("rtm", true)
- .Case("sahf", true)
.Case("sgx", true)
.Case("sha", true)
.Case("shstk", true)
@@ -1323,7 +1313,6 @@ bool X86TargetInfo::hasFeature(StringRef Feature) cons
.Case("retpoline", HasRetpoline)
.Case("retpoline-external-thunk", HasRetpolineExternalThunk)
.Case("rtm", HasRTM)
- .Case("sahf", HasLAHFSAHF)
.Case("sgx", HasSGX)
.Case("sha", HasSHA)
.Case("shstk", HasSHSTK)
Modified: head/contrib/llvm/tools/clang/lib/Basic/Targets/X86.h
==============================================================================
--- head/contrib/llvm/tools/clang/lib/Basic/Targets/X86.h Sat Apr 14 12:52:34 2018 (r332502)
+++ head/contrib/llvm/tools/clang/lib/Basic/Targets/X86.h Sat Apr 14 14:57:32 2018 (r332503)
@@ -98,7 +98,6 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public T
bool HasPREFETCHWT1 = false;
bool HasRetpoline = false;
bool HasRetpolineExternalThunk = false;
- bool HasLAHFSAHF = false;
/// \brief Enumeration of all of the X86 CPUs supported by Clang.
///
Modified: head/lib/clang/freebsd_cc_version.h
==============================================================================
--- head/lib/clang/freebsd_cc_version.h Sat Apr 14 12:52:34 2018 (r332502)
+++ head/lib/clang/freebsd_cc_version.h Sat Apr 14 14:57:32 2018 (r332503)
@@ -1,3 +1,3 @@
/* $FreeBSD$ */
-#define FREEBSD_CC_VERSION 1200012
+#define FREEBSD_CC_VERSION 1200013
Modified: head/lib/clang/libllvm/Makefile
==============================================================================
--- head/lib/clang/libllvm/Makefile Sat Apr 14 12:52:34 2018 (r332502)
+++ head/lib/clang/libllvm/Makefile Sat Apr 14 14:57:32 2018 (r332503)
@@ -1042,7 +1042,6 @@ SRCS_MIN+= Target/X86/X86FastISel.cpp
SRCS_MIN+= Target/X86/X86FixupBWInsts.cpp
SRCS_MIN+= Target/X86/X86FixupLEAs.cpp
SRCS_MIN+= Target/X86/X86FixupSetCC.cpp
-SRCS_MIN+= Target/X86/X86FlagsCopyLowering.cpp
SRCS_MIN+= Target/X86/X86FloatingPoint.cpp
SRCS_MIN+= Target/X86/X86FrameLowering.cpp
SRCS_MIN+= Target/X86/X86ISelDAGToDAG.cpp
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