svn commit: r332002 - in head/sys/arm/mv: . armada

[Marcin Wojtas]

Author: mw
Date: Wed Apr  4 10:14:43 2018
New Revision: 332002
URL: https://svnweb.freebsd.org/changeset/base/332002

Log:
  Make Marvell Armada reset registers usage generic
  
  Define reset registers for both Armada38X and ArmadaXP and
  choose proper one during runtime based on information from FDT.
  
  Submitted by: Rafal Kozik <rk at semihalf.com>
  Obtained from: Semihalf
  Sponsored by: Stormshield
  Differential Revision: https://reviews.freebsd.org/D14745

Modified:
  head/sys/arm/mv/armada/wdt.c
  head/sys/arm/mv/mv_armv7_machdep.c
  head/sys/arm/mv/mvreg.h
  head/sys/arm/mv/timer.c

Modified: head/sys/arm/mv/armada/wdt.c
==============================================================================
--- head/sys/arm/mv/armada/wdt.c	Wed Apr  4 09:11:15 2018	(r332001)
+++ head/sys/arm/mv/armada/wdt.c	Wed Apr  4 10:14:43 2018	(r332002)
@@ -245,9 +245,9 @@ mv_wdt_enable_armada_38x_xp_helper()
 	val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
 	write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
 
-	val = read_cpu_misc(RSTOUTn_MASK);
+	val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
 	val &= ~RSTOUTn_MASK_WD;
-	write_cpu_misc(RSTOUTn_MASK, val);
+	write_cpu_misc(RSTOUTn_MASK_ARMV7, val);
 }
 
 static void
@@ -305,9 +305,9 @@ mv_wdt_disable_armada_38x_xp_helper(void)
 	val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
 	write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
 
-	val = read_cpu_misc(RSTOUTn_MASK);
+	val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
 	val |= RSTOUTn_MASK_WD;
-	write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD);
+	write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD);
 }
 
 static void

Modified: head/sys/arm/mv/mv_armv7_machdep.c
==============================================================================
--- head/sys/arm/mv/mv_armv7_machdep.c	Wed Apr  4 09:11:15 2018	(r332001)
+++ head/sys/arm/mv/mv_armv7_machdep.c	Wed Apr  4 10:14:43 2018	(r332002)
@@ -439,8 +439,8 @@ static void
 mv_cpu_reset(platform_t plat)
 {
 
-	write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN);
-	write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
+	write_cpu_misc(RSTOUTn_MASK_ARMV7, SOFT_RST_OUT_EN_ARMV7);
+	write_cpu_misc(SYSTEM_SOFT_RESET_ARMV7, SYS_SOFT_RST_ARMV7);
 }
 
 #if defined(SOC_MV_ARMADA38X)

Modified: head/sys/arm/mv/mvreg.h
==============================================================================
--- head/sys/arm/mv/mvreg.h	Wed Apr  4 09:11:15 2018	(r332001)
+++ head/sys/arm/mv/mvreg.h	Wed Apr  4 10:14:43 2018	(r332002)
@@ -103,17 +103,15 @@
 /*
  * System reset
  */
-#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
-#define RSTOUTn_MASK		0x60
-#define SYSTEM_SOFT_RESET	0x64
-#define SOFT_RST_OUT_EN		0x00000001
-#define SYS_SOFT_RST		0x00000001
-#else
+#define	RSTOUTn_MASK_ARMV7	0x60
+#define	SYSTEM_SOFT_RESET_ARMV7	0x64
+#define	SOFT_RST_OUT_EN_ARMV7	0x00000001
+#define	SYS_SOFT_RST_ARMV7	0x00000001
+
 #define RSTOUTn_MASK		0x8
 #define SOFT_RST_OUT_EN		0x00000004
 #define SYSTEM_SOFT_RESET	0xc
 #define SYS_SOFT_RST		0x00000001
-#endif
 #define RSTOUTn_MASK_WD		0x400
 #define WD_RSTOUTn_MASK		0x4
 #define WD_GLOBAL_MASK		0x00000100

Modified: head/sys/arm/mv/timer.c
==============================================================================
--- head/sys/arm/mv/timer.c	Wed Apr  4 09:11:15 2018	(r332001)
+++ head/sys/arm/mv/timer.c	Wed Apr  4 10:14:43 2018	(r332002)
@@ -411,9 +411,9 @@ mv_watchdog_enable_armadaxp(void)
 	val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
 	write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
 
-	val = read_cpu_misc(RSTOUTn_MASK);
+	val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
 	val &= ~RSTOUTn_MASK_WD;
-	write_cpu_misc(RSTOUTn_MASK, val);
+	write_cpu_misc(RSTOUTn_MASK_ARMV7, val);
 
 	val = mv_get_timer_control();
 	val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;
@@ -451,9 +451,9 @@ mv_watchdog_disable_armadaxp(void)
 	val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
 	write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
 
-	val = read_cpu_misc(RSTOUTn_MASK);
+	val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
 	val |= RSTOUTn_MASK_WD;
-	write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD);
+	write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD);
 
 	irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 	irq_cause &= IRQ_TIMER_WD_CLR;