svn commit: r323288 - in head/sys/x86: include x86

[Conrad Meyer]

Author: cem
Date: Thu Sep  7 21:31:07 2017
New Revision: 323288
URL: https://svnweb.freebsd.org/changeset/base/323288

Log:
  x86 MCA: Enable AMD thresholding support on 17h
  
  17h supports MCA thresholding in the same way as 16h and earlier.
  Supposedly a ScalableMca feature bit in CPUID 8000_0007:EBX must be set, but
  that was not true for earlier models, so be careful about relying on it.
  
  While here, document a missing bit in LS MCA MISC0.
  
  Reviewed by:	truckman
  Sponsored by:	Dell EMC Isilon
  Differential Revision:	https://reviews.freebsd.org/D12237

Modified:
  head/sys/x86/include/specialreg.h
  head/sys/x86/x86/mca.c

Modified: head/sys/x86/include/specialreg.h
==============================================================================
--- head/sys/x86/include/specialreg.h	Thu Sep  7 21:29:51 2017	(r323287)
+++ head/sys/x86/include/specialreg.h	Thu Sep  7 21:31:07 2017	(r323288)
@@ -718,6 +718,7 @@
 #define	MC_MISC_AMDNB_VAL	0x8000000000000000	/* Counter presence valid */
 #define	MC_MISC_AMDNB_CNTP	0x4000000000000000	/* Counter present */
 #define	MC_MISC_AMDNB_LOCK	0x2000000000000000	/* Register locked */
+#define	MC_MISC_AMDNB_INTP	0x1000000000000000	/* Int. type can generate interrupts */
 #define	MC_MISC_AMDNB_LVT_MASK	0x00f0000000000000	/* Extended LVT offset */
 #define	MC_MISC_AMDNB_LVT_SHIFT	52
 #define	MC_MISC_AMDNB_CNTEN	0x0008000000000000	/* Counter enabled */

Modified: head/sys/x86/x86/mca.c
==============================================================================
--- head/sys/x86/x86/mca.c	Thu Sep  7 21:29:51 2017	(r323287)
+++ head/sys/x86/x86/mca.c	Thu Sep  7 21:31:07 2017	(r323288)
@@ -132,8 +132,20 @@ static int amd_elvt = -1;
 static inline bool
 amd_thresholding_supported(void)
 {
-	return (cpu_vendor_id == CPU_VENDOR_AMD &&
-	    CPUID_TO_FAMILY(cpu_id) >= 0x10 && CPUID_TO_FAMILY(cpu_id) <= 0x16);
+	if (cpu_vendor_id != CPU_VENDOR_AMD)
+		return (false);
+	/*
+	 * The RASCap register is wholly reserved in families 0x10-0x15 (through model 1F).
+	 *
+	 * It begins to be documented in family 0x15 model 30 and family 0x16,
+	 * but neither of these families documents the ScalableMca bit, which
+	 * supposedly defines the presence of this feature on family 0x17.
+	 */
+	if (CPUID_TO_FAMILY(cpu_id) >= 0x10 && CPUID_TO_FAMILY(cpu_id) <= 0x16)
+		return (true);
+	if (CPUID_TO_FAMILY(cpu_id) >= 0x17)
+		return ((amd_rascap & AMDRAS_SCALABLE_MCA) != 0);
+	return (false);
 }
 #endif