svn commit: r323233 - head/sys/dev/bnxt
Stephen Hurd
shurd at FreeBSD.org
Wed Sep 6 20:19:32 UTC 2017
Author: shurd
Date: Wed Sep 6 20:19:30 2017
New Revision: 323233
URL: https://svnweb.freebsd.org/changeset/base/323233
Log:
bnxt: Update firmware header file with the latest one
hsi_struct_def.h file contains all firmware (HWRM) data struct's, updated
that with the latest one which was released on 30'th Aug.
After this upgrade, HWRM version will be 1.8.1.5 (earlier it was 1.4.0).
Submitted by: Bhargava Chenna Marreddy <bhargava.marreddy at broadcom.com>
Reviewed by: shurd, sbruno
Approved by: sbruno (mentor)
Sponsored by: Broadcom Limited
Differential Revision: https://reviews.freebsd.org/D12203
Modified:
head/sys/dev/bnxt/bnxt_hwrm.c
head/sys/dev/bnxt/hsi_struct_def.h
head/sys/dev/bnxt/if_bnxt.c
Modified: head/sys/dev/bnxt/bnxt_hwrm.c
==============================================================================
--- head/sys/dev/bnxt/bnxt_hwrm.c Wed Sep 6 20:14:34 2017 (r323232)
+++ head/sys/dev/bnxt/bnxt_hwrm.c Wed Sep 6 20:19:30 2017 (r323233)
@@ -1478,12 +1478,12 @@ bnxt_hwrm_port_phy_qcfg(struct bnxt_softc *softc)
goto exit;
link_info->phy_link_status = resp->link;
- link_info->duplex = resp->duplex;
+ link_info->duplex = resp->duplex_cfg;
link_info->pause = resp->pause;
link_info->auto_mode = resp->auto_mode;
link_info->auto_pause = resp->auto_pause;
link_info->force_pause = resp->force_pause;
- link_info->duplex_setting = resp->duplex;
+ link_info->duplex_setting = resp->duplex_cfg;
if (link_info->phy_link_status == HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK)
link_info->link_speed = le16toh(resp->link_speed);
else
Modified: head/sys/dev/bnxt/hsi_struct_def.h
==============================================================================
--- head/sys/dev/bnxt/hsi_struct_def.h Wed Sep 6 20:14:34 2017 (r323232)
+++ head/sys/dev/bnxt/hsi_struct_def.h Wed Sep 6 20:19:30 2017 (r323233)
@@ -34,7 +34,7 @@ __FBSDID("$FreeBSD$");
*
* Description: Definition of HSI data structures
*
- * Date: 07/26/16 21:30:37
+ * Date: 08/31/17 17:55:46
*
* Note: This file is scripted generated by hsi_decode.py.
* DO NOT modify this file manually !!!!
@@ -42,35 +42,45 @@ __FBSDID("$FreeBSD$");
****************************************************************************/
#ifndef _HSI_STRUCT_DEF_EXTERNAL_H_
#define _HSI_STRUCT_DEF_EXTERNAL_H_
+/* HSI and HWRM Specification 1.8.1 */
+#define HWRM_VERSION_MAJOR 1
+#define HWRM_VERSION_MINOR 8
+#define HWRM_VERSION_UPDATE 1
+#define HWRM_VERSION_RSVD 7
+
+#define HWRM_VERSION_STR "1.8.1.7"
/*
- * per-context HW statistics -- chip view
- * Reference to stat_ctx_stat_xxx for
+ * Following is the signature for HWRM message field that indicates not
+ * applicable (All F's). Need to cast it the size of the field if needed.
*/
+#define HWRM_NA_SIGNATURE ((uint32_t)(-1))
+#define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */
+#define HWRM_MAX_RESP_LEN (272) /* hwrm_selftest_qlist */
+#define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */
+#define HW_HASH_KEY_SIZE 40
+#define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */
+#define ROCE_SP_HSI_VERSION_MAJOR 1
+#define ROCE_SP_HSI_VERSION_MINOR 8
+#define ROCE_SP_HSI_VERSION_UPDATE 1
-struct ctx_hw_stats {
- uint64_t rx_ucast_pkts;
- uint64_t rx_mcast_pkts;
- uint64_t rx_bcast_pkts;
- uint64_t rx_discard_pkts;
- uint64_t rx_drop_pkts;
- uint64_t rx_ucast_bytes;
- uint64_t rx_mcast_bytes;
- uint64_t rx_bcast_bytes;
- uint64_t tx_ucast_pkts;
- uint64_t tx_mcast_pkts;
- uint64_t tx_bcast_pkts;
- uint64_t tx_discard_pkts;
- uint64_t tx_drop_pkts;
- uint64_t tx_ucast_bytes;
- uint64_t tx_mcast_bytes;
- uint64_t tx_bcast_bytes;
- uint64_t tpa_pkts;
- uint64_t tpa_bytes;
- uint64_t tpa_events;
- uint64_t tpa_aborts;
-} __attribute__((packed));
-
+#define ROCE_SP_HSI_VERSION_STR "1.8.1"
+/*
+ * Following is the signature for ROCE_SP_HSI message field that indicates not
+ * applicable (All F's). Need to cast it the size of the field if needed.
+ */
+#define ROCE_SP_HSI_NA_SIGNATURE ((uint32_t)(-1))
+/*
+ * Note: The Host Software Interface (HSI) and Hardware Resource Manager (HWRM)
+ * specification describes the data structures used in Ethernet packet or RDMA
+ * message data transfers as well as an abstract interface for managing Ethernet
+ * NIC hardware resources.
+ */
+/* Ethernet Data path Host Structures */
+/*
+ * Description: The following three sections document the host structures used
+ * between device and software drivers for communicating Ethernet packets.
+ */
/* BD Ring Structures */
/*
* Description: This structure is used to inform the NIC of a location for and
@@ -845,6 +855,7 @@ struct rx_pkt_cmpl {
/* This bit is '1' if the RSS field in this completion is valid. */
#define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
/* unused is 1 b */
+ #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
/*
* This value indicates what the inner packet determined for the packet
* was.
@@ -931,7 +942,27 @@ struct rx_pkt_cmpl {
uint8_t rss_hash_type;
/*
* This is the RSS hash type for the packet. The value is packed
- * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
+ * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. The
+ * value of tuple_extrac_op provides the information about what fields
+ * the hash was computed on. * 0: The RSS hash was computed over source
+ * IP address, destination IP address, source port, and destination port
+ * of inner IP and TCP or UDP headers. Note: For non-tunneled packets,
+ * the packet headers are considered inner packet headers for the RSS
+ * hash computation purpose. * 1: The RSS hash was computed over source
+ * IP address and destination IP address of inner IP header. Note: For
+ * non-tunneled packets, the packet headers are considered inner packet
+ * headers for the RSS hash computation purpose. * 2: The RSS hash was
+ * computed over source IP address, destination IP address, source port,
+ * and destination port of IP and TCP or UDP headers of outer tunnel
+ * headers. Note: For non-tunneled packets, this value is not
+ * applicable. * 3: The RSS hash was computed over source IP address and
+ * destination IP address of IP header of outer tunnel headers. Note:
+ * For non-tunneled packets, this value is not applicable. Note that
+ * 4-tuples values listed above are applicable for layer 4 protocols
+ * supported and enabled for RSS in the hardware, HWRM firmware, and
+ * drivers. For example, if RSS hash is supported and enabled for TCP
+ * traffic only, then the values of tuple_extract_op corresponding to
+ * 4-tuples are only valid for TCP traffic.
*/
uint8_t payload_offset;
/*
@@ -1234,6 +1265,7 @@ struct rx_tpa_start_cmpl {
/* This bit is '1' if the RSS field in this completion is valid. */
#define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
/* unused is 1 b */
+ #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
/*
* This value indicates what the inner packet determined for the packet
* was.
@@ -1267,7 +1299,27 @@ struct rx_tpa_start_cmpl {
uint8_t rss_hash_type;
/*
* This is the RSS hash type for the packet. The value is packed
- * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
+ * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. The
+ * value of tuple_extrac_op provides the information about what fields
+ * the hash was computed on. * 0: The RSS hash was computed over source
+ * IP address, destination IP address, source port, and destination port
+ * of inner IP and TCP or UDP headers. Note: For non-tunneled packets,
+ * the packet headers are considered inner packet headers for the RSS
+ * hash computation purpose. * 1: The RSS hash was computed over source
+ * IP address and destination IP address of inner IP header. Note: For
+ * non-tunneled packets, the packet headers are considered inner packet
+ * headers for the RSS hash computation purpose. * 2: The RSS hash was
+ * computed over source IP address, destination IP address, source port,
+ * and destination port of IP and TCP or UDP headers of outer tunnel
+ * headers. Note: For non-tunneled packets, this value is not
+ * applicable. * 3: The RSS hash was computed over source IP address and
+ * destination IP address of IP header of outer tunnel headers. Note:
+ * For non-tunneled packets, this value is not applicable. Note that
+ * 4-tuples values listed above are applicable for layer 4 protocols
+ * supported and enabled for RSS in the hardware, HWRM firmware, and
+ * drivers. For example, if RSS hash is supported and enabled for TCP
+ * traffic only, then the values of tuple_extract_op corresponding to
+ * 4-tuples are only valid for TCP traffic.
*/
uint16_t agg_id;
/*
@@ -1456,6 +1508,8 @@ struct rx_tpa_end_cmpl {
#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS (UINT32_C(0x6) << 7)
#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
/* unused is 2 b */
+ #define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
+ #define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10
/*
* This value indicates what the inner packet determined for the packet
* was. - 2 TCP Packet Indicates that the packet was IP and TCP. This
@@ -1794,6 +1848,7 @@ struct hwrm_fwd_resp_cmpl {
((x) == 0x33 ? "VF_CFG_CHANGE": \
((x) == 0x11 ? "FUNC_DRVR_LOAD": \
((x) == 0x31 ? "VF_MAC_ADDR_CHANGE": \
+ ((x) == 0x34 ? "LLFC_PFC_CHANGE": \
((x) == 0x4 ? "PORT_CONN_NOT_ALLOWED": \
((x) == 0x5 ? "LINK_SPEED_CFG_NOT_ALLOWED": \
((x) == 0x6 ? "LINK_SPEED_CFG_CHANGE": \
@@ -1804,7 +1859,7 @@ struct hwrm_fwd_resp_cmpl {
((x) == 0x3 ? "DCB_CONFIG_CHANGE": \
((x) == 0x12 ? "FUNC_FLR_PROC_CMPLT": \
((x) == 0x21 ? "PF_DRVR_LOAD": \
- "Unknown event_id"))))))))))))))))))
+ "Unknown event_id")))))))))))))))))))
/* HWRM Asynchronous Event Completion Record (16 bytes) */
@@ -1857,6 +1912,8 @@ struct hwrm_async_event_cmpl {
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE UINT32_C(0x32)
/* VF Configuration Change */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE UINT32_C(0x33)
+ /* LLFC/PFC Configuration Change */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE UINT32_C(0x34)
/* HWRM Error */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR UINT32_C(0xff)
uint32_t event_data2;
@@ -2075,6 +2132,12 @@ struct hwrm_async_event_cmpl_dcb_config_change {
#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE UINT32_C(0x3)
uint32_t event_data2;
/* Event specific data */
+ /* ETS configuration change */
+ #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS UINT32_C(0x1)
+ /* PFC configuration change */
+ #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC UINT32_C(0x2)
+ /* APP configuration change */
+ #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP UINT32_C(0x4)
uint8_t opaque_v;
/* opaque is 7 b */
/*
@@ -2095,6 +2158,18 @@ struct hwrm_async_event_cmpl_dcb_config_change {
/* PORT ID */
#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff)
#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
+ /* Priority recommended for RoCE traffic */
+ #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK UINT32_C(0xff0000)
+ #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT 16
+ /* none is 255 */
+ #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE (UINT32_C(0xff) << 16)
+ #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
+ /* Priority recommended for L2 traffic */
+ #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK UINT32_C(0xff000000)
+ #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT 24
+ /* none is 255 */
+ #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE (UINT32_C(0xff) << 24)
+ #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
} __attribute__((packed));
/* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */
@@ -2733,6 +2808,60 @@ struct hwrm_async_event_cmpl_vf_cfg_change {
#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE UINT32_C(0x8)
} __attribute__((packed));
+/* HWRM Asynchronous Event Completion Record for llfc pfc status change (16 bytes) */
+
+struct hwrm_async_event_cmpl_llfc_pfc_change {
+ uint16_t type;
+ /* unused1 is 10 b */
+ /*
+ * This field indicates the exact type of the completion. By convention,
+ * the LSB identifies the length of the record in 16B units. Even values
+ * indicate 16B records. Odd values indicate 32B records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
+ /* unused1 is 10 b */
+ uint16_t event_id;
+ /* Identifiers of events. */
+ /* LLFC/PFC Configuration Change */
+ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE UINT32_C(0x34)
+ uint32_t event_data2;
+ /* Event specific data */
+ uint8_t opaque_v;
+ /* opaque is 7 b */
+ /*
+ * This value is written by the NIC such that it will be different for
+ * each pass through the completion queue. The even passes will write 1.
+ * The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
+ uint8_t timestamp_lo;
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint32_t event_data1;
+ /* Event specific data */
+ /* Indicates llfc pfc status change */
+ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK UINT32_C(0x3)
+ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT 0
+ /* If this field set to 1, then it indicates that llfc is enabled. */
+ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC (UINT32_C(0x1) << 0)
+ /* If this field is set to 2, then it indicates that pfc is enabled. */
+ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC (UINT32_C(0x2) << 0)
+ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
+ /* Indicates the physical port this llfc pfc change occur */
+ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK UINT32_C(0x1c)
+ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT 2
+ /* PORT ID */
+ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0x1fffe0)
+ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT 5
+} __attribute__((packed));
+
/* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */
struct hwrm_async_event_cmpl_hwrm_error {
@@ -3205,758 +3334,2126 @@ struct push32_doorbell {
*/
} __attribute__((packed));
-/* HW Resource Manager Specification 1.4.0 */
-#define HWRM_VERSION_MAJOR 1
-#define HWRM_VERSION_MINOR 4
-#define HWRM_VERSION_UPDATE 0
-
-#define HWRM_VERSION_STR "1.4.0"
+/* Doorbell Structures */
/*
- * Following is the signature for HWRM message field that indicates not
- * applicable (All F's). Need to cast it the size of the field if needed.
+ * Description: This is the RoCE 32b Doorbell format. The host writes this
+ * message format directly to byte offset 8 of the appropriate doorbell page.
*/
-#define HWRM_NA_SIGNATURE ((uint32_t)(-1))
-#define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */
-#define HWRM_MAX_RESP_LEN (176) /* hwrm_func_qstats */
-#define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */
-#define HW_HASH_KEY_SIZE 40
-#define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */
+/* 64b Doorbell Format (8 bytes) */
+
+struct dbr_dbr {
+ uint32_t index;
+ /*
+ * This value is the index being written. For SQ, RQ, SRQ, this is the
+ * producer index and should be the queue index of the last WQE written
+ * plus 1. For CQ, this is the consumer index and should be the index of
+ * the last CQE processed plus 1.
+ */
+ #define DBR_DBR_INDEX_MASK UINT32_C(0xfffff)
+ #define DBR_DBR_INDEX_SFT 0
+ #define DBR_DBR_RESERVED12_MASK UINT32_C(0xfff00000)
+ #define DBR_DBR_RESERVED12_SFT 20
+ uint32_t type_xid;
+ /* This value identifies the type of doorbell being written. */
+ /*
+ * This value identifies the resource that the doorbell is intended to
+ * notify. For SQ and RQ, this is the QPID. For SRQ, this is the SID.
+ * For CQ, this is the CID. Bits [19:16] of this values must be zero for
+ * a SID value.
+ */
+ #define DBR_DBR_XID_MASK UINT32_C(0xfffff)
+ #define DBR_DBR_XID_SFT 0
+ #define DBR_DBR_RESERVED8_MASK UINT32_C(0xff00000)
+ #define DBR_DBR_RESERVED8_SFT 20
+ /* This value identifies the type of doorbell being written. */
+ #define DBR_DBR_TYPE_MASK UINT32_C(0xf0000000)
+ #define DBR_DBR_TYPE_SFT 28
+ /*
+ * This is a SQ producer index update. It indicates one or more
+ * new entries have been written to the SQ for the QPID
+ * indicated on the xID field.
+ */
+ #define DBR_DBR_TYPE_SQ (UINT32_C(0x0) << 28)
+ /*
+ * This is a RQ producer index update. It indicates one or more
+ * new entries have been written to the RQ for the QPID
+ * indicated on the xID field.
+ */
+ #define DBR_DBR_TYPE_RQ (UINT32_C(0x1) << 28)
+ /*
+ * This is a SRQ producer index update. It indicates one or more
+ * new entries have been written to the SRQ for the SID
+ * indicated on the xID field.
+ */
+ #define DBR_DBR_TYPE_SRQ (UINT32_C(0x2) << 28)
+ /*
+ * This doorbell command arms the SRQ async event. The xID field
+ * must identify the SID that is begin armed. The index field is
+ * will set the arm threshold such that a notification will be
+ * generated if less than that number or SRQ entries are posted.
+ */
+ #define DBR_DBR_TYPE_SRQ_ARM (UINT32_C(0x3) << 28)
+ /*
+ * This is a CQ consumer index update. It indicates one or more
+ * entries have been processed off the CQ indicated on the xID
+ * field.
+ */
+ #define DBR_DBR_TYPE_CQ (UINT32_C(0x4) << 28)
+ /*
+ * this is a CQ consumer index update that also arms the CQ for
+ * solicited events.
+ */
+ #define DBR_DBR_TYPE_CQ_ARMSE (UINT32_C(0x5) << 28)
+ /*
+ * This is a CQ consumer index update that also arms the CQ for
+ * any new CQE.
+ */
+ #define DBR_DBR_TYPE_CQ_ARMALL (UINT32_C(0x6) << 28)
+ /*
+ * This is a CQ arm enable message. This message must be sent
+ * from the privileged driver before a new CQ_ARMSE or CQ_ARMALL
+ * message will be accepted. This doorbell can only be sent from
+ * the privileged (first) doorbell page of a function.
+ */
+ #define DBR_DBR_TYPE_CQ_ARMENA (UINT32_C(0x7) << 28)
+ /*
+ * This doorbell command enables the SRQ async event to be
+ * armed. This message must be setn from the privileged driver
+ * before a new SRQ_ARM message will be accepted. The xID field
+ * must identify the SID that is begin enabled for arm. This
+ * doorbell can only be sent from the privileged (first)
+ * doorbell page of a function.
+ */
+ #define DBR_DBR_TYPE_SRQ_ARMENA (UINT32_C(0x8) << 28)
+ /*
+ * This doorbell command indicates that the cutoff CQE has been
+ * processed and the driver is now processing completions from
+ * the new CQ. The index field for this doorbell type must be
+ * zero.
+ */
+ #define DBR_DBR_TYPE_CQ_CUTOFF_ACK (UINT32_C(0x9) << 28)
+ /*
+ * This doorbell command is used during doorbell moderation to
+ * consume system BW and help prevent doorbell FIFO overflow.
+ * All other fields should be zero for NULL doorbell.
+ */
+ #define DBR_DBR_TYPE_NULL (UINT32_C(0xf) << 28)
+} __attribute__((packed));
+
+/* 32b Doorbell Format (4 bytes) */
+
+struct dbr_dbr32 {
+ uint32_t type_abs_incr_xid;
+ /* This value identifies the type of doorbell being written. */
+ /*
+ * This value identifies the resource that the doorbell is intended to
+ * notify. For SQ and RQ, this is the QPID. For SRQ, this is the SID.
+ * For CQ, this is the CID. Bits [19:16] of this values must be zero for
+ * a SID value.
+ */
+ #define DBR_DBR32_XID_MASK UINT32_C(0xfffff)
+ #define DBR_DBR32_XID_SFT 0
+ #define DBR_DBR32_RESERVED4_MASK UINT32_C(0xf00000)
+ #define DBR_DBR32_RESERVED4_SFT 20
+ /*
+ * When abs=0, this value is the value to add to the appropriate index
+ * value. When abs=1, this value is the new value for the index.
+ * Absolute value is used when the queue is being wrapped. When abs=1,
+ * the incr value follows the same rules as the index value in the 64b
+ * doorbell.
+ */
+ #define DBR_DBR32_INCR_MASK UINT32_C(0xf000000)
+ #define DBR_DBR32_INCR_SFT 24
+ /* This value defines how the incr value will be interpreted. */
+ #define DBR_DBR32_ABS UINT32_C(0x10000000)
+ /* This value identifies the type of doorbell being written. */
+ #define DBR_DBR32_TYPE_MASK UINT32_C(0xe0000000)
+ #define DBR_DBR32_TYPE_SFT 29
+ /*
+ * This is a SQ producer index update. It indicates one or more
+ * new entries have been written to the SQ for the QPID
+ * indicated on the xID field.
+ */
+ #define DBR_DBR32_TYPE_SQ (UINT32_C(0x0) << 29)
+} __attribute__((packed));
+
+/* SQ WQE Structures */
/*
- * Description: Port Rx Statistics Formats. The HWRM shall return any
- * unsupported counter with a value of 0xFFFFFFFF for 32-bit counters and
- * 0xFFFFFFFFFFFFFFFF for 64-bit counters.
+ * Description: This is the Bind WQE structure. This WQE can perform either: *
+ * type1 "bind memory window", if mw_type==Type1 * type2 "post send bind memory
+ * window", if mw_type==Type2
*/
-/*
- * Note: The Hardware Resource Manager (HWRM) manages various hardware resources
- * inside the chip. The HWRM is implemented in firmware, and runs on embedded
- * processors inside the chip. This firmware service is vital part of the chip.
- * The chip can not be used by a driver or HWRM client without the HWRM.
- */
-/* Input (16 bytes) */
+/* Base SQ WQE (8 bytes) */
-struct input {
- uint16_t req_type;
+struct sq_base {
+ uint8_t wqe_type;
+ /* This field defines the type of SQ WQE. */
+ /* Send */
+ #define SQ_BASE_WQE_TYPE_SEND UINT32_C(0x0)
/*
- * This value indicates what type of request this is. The format for the
- * rest of the command is determined by this field.
+ * Send with Immediate Allowed only on reliable connection (RC)
+ * and unreliable datagram (UD) SQ's.
*/
- uint16_t cmpl_ring;
+ #define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD UINT32_C(0x1)
/*
- * This value indicates the what completion ring the request will be
- * optionally completed on. If the value is -1, then no CR completion
- * will be generated. Any other value must be a valid CR ring_id value
- * for this function.
+ * Send with Invalidate. Allowed only on reliable connection
+ * (RC) SQ's.
*/
- uint16_t seq_id;
- /* This value indicates the command sequence number. */
- uint16_t target_id;
+ #define SQ_BASE_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2)
+ /* RDMA Write. Allowed only on reliable connection (RC) SQ's. */
+ #define SQ_BASE_WQE_TYPE_WRITE_WQE UINT32_C(0x4)
/*
- * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
- * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
+ * RDMA Write with Immediate. Allowed only on reliable
+ * connection (RC) SQ's.
*/
- uint64_t resp_addr;
+ #define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5)
+ /* RDMA Read. Allowed only on reliable connection (RC) SQ's. */
+ #define SQ_BASE_WQE_TYPE_READ_WQE UINT32_C(0x6)
/*
- * This is the host address where the response will be written when the
- * request is complete. This area must be 16B aligned and must be
- * cleared to zero before the request is made.
+ * Atomic Compare/Swap. Allowed only on reliable connection (RC)
+ * SQ's.
*/
+ #define SQ_BASE_WQE_TYPE_ATOMIC_CS UINT32_C(0x8)
+ /* Atomic Fetch/Add. Allowed only on reliable connection (RC) SQ's. */
+ #define SQ_BASE_WQE_TYPE_ATOMIC_FA UINT32_C(0xb)
+ /* Local Invalidate. Allowed only on reliable connection (RC) SQ's. */
+ #define SQ_BASE_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc)
+ /*
+ * FR-PMR (Fast Register Physical Memory Region) Allowed only on
+ * reliable connection (RC) SQ's.
+ */
+ #define SQ_BASE_WQE_TYPE_FR_PMR UINT32_C(0xd)
+ /* Memory Bind Allowed only on reliable connection (RC) SQ's. */
+ #define SQ_BASE_WQE_TYPE_BIND UINT32_C(0xe)
+ uint8_t unused_0[7];
} __attribute__((packed));
-/* Output (8 bytes) */
+/* WQE SGE (16 bytes) */
-struct output {
- uint16_t error_code;
+struct sq_sge {
+ uint64_t va_or_pa;
/*
- * Pass/Fail or error type Note: receiver to verify the in parameters,
- * and fail the call with an error when appropriate
+ * The virtual address in local memory or a physical address when l_key
+ * value is a reserved value of a physical address. Driver configures
+ * this value in the chip and the chip compares l_key in SGEs with that
+ * reserved value, if equal it access the physical address specified.
+ * The chip however MUST verify that the QP allows the use reserved key.
*/
- uint16_t req_type;
- /* This field returns the type of original request. */
- uint16_t seq_id;
- /* This field provides original sequence number of the command. */
- uint16_t resp_len;
+ uint32_t l_key;
/*
- * This field is the length of the response in bytes. The last byte of
- * the response is a valid flag that will read as '1' when the command
- * has been completely written to memory.
+ * Local Key associated with this registered MR; The 24 msb of the key
+ * used to index the MRW Table and the 8 lsb are compared with the 8
+ * bits key part stored in the MRWC. The PBL in the MRW Context is used
+ * to translate the above VA to physical address.
*/
+ uint32_t size;
+ /*
+ * Size of SGE in bytes; Based on page size of the system the chip knows
+ * how many entries are in the PBL
+ */
} __attribute__((packed));
-#define GET_HWRM_REQ_TYPE(x) \
- ((x) == 0x98 ? "HWRM_CFA_ENCAP_RECORD_FREE": \
- ((x) == 0x99 ? "HWRM_CFA_NTUPLE_FILTER_ALLOC": \
- ((x) == 0x90 ? "HWRM_CFA_L2_FILTER_ALLOC": \
- ((x) == 0x91 ? "HWRM_CFA_L2_FILTER_FREE": \
- ((x) == 0x92 ? "HWRM_CFA_L2_FILTER_CFG": \
- ((x) == 0x93 ? "HWRM_CFA_L2_SET_RX_MASK": \
- ((x) == 0x94 ? "RESERVED3": \
- ((x) == 0x95 ? "HWRM_CFA_TUNNEL_FILTER_ALLOC": \
- ((x) == 0x96 ? "HWRM_CFA_TUNNEL_FILTER_FREE": \
- ((x) == 0x97 ? "HWRM_CFA_ENCAP_RECORD_ALLOC": \
- ((x) == 0x10 ? "RESERVED1": \
- ((x) == 0x11 ? "HWRM_FUNC_RESET": \
- ((x) == 0x12 ? "HWRM_FUNC_GETFID": \
- ((x) == 0x13 ? "HWRM_FUNC_VF_ALLOC": \
- ((x) == 0x14 ? "HWRM_FUNC_VF_FREE": \
- ((x) == 0x15 ? "HWRM_FUNC_QCAPS": \
- ((x) == 0x16 ? "HWRM_FUNC_QCFG": \
- ((x) == 0x17 ? "HWRM_FUNC_CFG": \
- ((x) == 0x18 ? "HWRM_FUNC_QSTATS": \
- ((x) == 0x19 ? "HWRM_FUNC_CLR_STATS": \
- ((x) == 0xe0 ? "HWRM_TEMP_MONITOR_QUERY": \
- ((x) == 0xd3 ? "HWRM_FWD_ASYNC_EVENT_CMPL": \
- ((x) == 0xd2 ? "HWRM_FWD_RESP": \
- ((x) == 0x1a ? "HWRM_FUNC_DRV_UNRGTR": \
- ((x) == 0x1b ? "HWRM_FUNC_VF_RESC_FREE": \
- ((x) == 0x1c ? "HWRM_FUNC_VF_VNIC_IDS_QUERY": \
- ((x) == 0x1d ? "HWRM_FUNC_DRV_RGTR": \
- ((x) == 0x1e ? "HWRM_FUNC_DRV_QVER": \
- ((x) == 0x1f ? "HWRM_FUNC_BUF_RGTR": \
- ((x) == 0x9a ? "HWRM_CFA_NTUPLE_FILTER_FREE": \
- ((x) == 0x9b ? "HWRM_CFA_NTUPLE_FILTER_CFG": \
- ((x) == 0x9c ? "HWRM_CFA_EM_FLOW_ALLOC": \
- ((x) == 0x9d ? "HWRM_CFA_EM_FLOW_FREE": \
- ((x) == 0x9e ? "HWRM_CFA_EM_FLOW_CFG": \
- ((x) == 0xd1 ? "HWRM_REJECT_FWD_RESP": \
- ((x) == 0xd0 ? "HWRM_EXEC_FWD_RESP": \
- ((x) == 0xc8 ? "HWRM_FW_SET_TIME": \
- ((x) == 0xc9 ? "HWRM_FW_GET_TIME": \
- ((x) == 0xc0 ? "HWRM_FW_RESET": \
- ((x) == 0xc1 ? "HWRM_FW_QSTATUS": \
- ((x) == 0x70 ? "HWRM_VNIC_RSS_COS_LB_CTX_ALLOC": \
- ((x) == 0x71 ? "HWRM_VNIC_RSS_COS_LB_CTX_FREE": \
- ((x) == 0xb1 ? "HWRM_STAT_CTX_FREE": \
- ((x) == 0xb0 ? "HWRM_STAT_CTX_ALLOC": \
- ((x) == 0xb3 ? "HWRM_STAT_CTX_CLR_STATS": \
- ((x) == 0xb2 ? "HWRM_STAT_CTX_QUERY": \
- ((x) == 0xfff6 ? "HWRM_NVM_GET_DEV_INFO": \
- ((x) == 0x61 ? "HWRM_RING_GRP_FREE": \
- ((x) == 0x60 ? "HWRM_RING_GRP_ALLOC": \
- ((x) == 0xf1 ? "HWRM_WOL_FILTER_FREE": \
- ((x) == 0xf0 ? "HWRM_WOL_FILTER_ALLOC": \
- ((x) == 0xf3 ? "HWRM_WOL_REASON_QCFG": \
- ((x) == 0xf2 ? "HWRM_WOL_FILTER_QCFG": \
- ((x) == 0xa0 ? "HWRM_TUNNEL_DST_PORT_QUERY": \
- ((x) == 0xa1 ? "HWRM_TUNNEL_DST_PORT_ALLOC": \
- ((x) == 0xa2 ? "HWRM_TUNNEL_DST_PORT_FREE": \
- ((x) == 0xfffc ? "HWRM_NVM_RAW_DUMP": \
- ((x) == 0xfffb ? "HWRM_NVM_GET_DIR_INFO": \
- ((x) == 0xfffa ? "HWRM_NVM_GET_DIR_ENTRIES": \
- ((x) == 0xe ? "HWRM_FUNC_BUF_UNRGTR": \
- ((x) == 0xf ? "HWRM_FUNC_VF_CFG": \
- ((x) == 0xffff ? "HWRM_NVM_RAW_WRITE_BLK": \
- ((x) == 0xfffe ? "HWRM_NVM_WRITE": \
- ((x) == 0xfffd ? "HWRM_NVM_READ": \
- ((x) == 0x50 ? "HWRM_RING_ALLOC": \
- ((x) == 0x51 ? "HWRM_RING_FREE": \
- ((x) == 0x52 ? "HWRM_RING_CMPL_RING_QAGGINT_PARAMS": \
- ((x) == 0x53 ? "HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS": \
- ((x) == 0x4a ? "HWRM_VNIC_QCAPS": \
- ((x) == 0x49 ? "HWRM_VNIC_PLCMODES_QCFG": \
- ((x) == 0x48 ? "HWRM_VNIC_PLCMODES_CFG": \
- ((x) == 0x47 ? "HWRM_VNIC_RSS_QCFG": \
- ((x) == 0x46 ? "HWRM_VNIC_RSS_CFG": \
- ((x) == 0x45 ? "HWRM_VNIC_TPA_QCFG": \
- ((x) == 0x44 ? "HWRM_VNIC_TPA_CFG": \
- ((x) == 0x43 ? "HWRM_VNIC_QCFG": \
- ((x) == 0x42 ? "HWRM_VNIC_CFG": \
- ((x) == 0x41 ? "HWRM_VNIC_FREE": \
- ((x) == 0x40 ? "HWRM_VNIC_ALLOC": \
- ((x) == 0x0 ? "HWRM_VER_GET": \
- ((x) == 0xfff9 ? "HWRM_NVM_FIND_DIR_ENTRY": \
- ((x) == 0xfff8 ? "HWRM_NVM_MOD_DIR_ENTRY": \
- ((x) == 0xfff7 ? "HWRM_NVM_ERASE_DIR_ENTRY": \
- ((x) == 0x5e ? "HWRM_RING_RESET": \
- ((x) == 0xfff5 ? "HWRM_NVM_VERIFY_UPDATE": \
- ((x) == 0xfff4 ? "HWRM_NVM_MODIFY": \
- ((x) == 0xfff3 ? "HWRM_NVM_INSTALL_UPDATE": \
- ((x) == 0x2a ? "HWRM_PORT_PHY_QCAPS": \
- ((x) == 0x2c ? "HWRM_PORT_PHY_I2C_READ": \
- ((x) == 0x2b ? "HWRM_PORT_PHY_I2C_WRITE": \
- ((x) == 0x38 ? "HWRM_QUEUE_PRI2COS_CFG": \
- ((x) == 0x39 ? "HWRM_QUEUE_COS2BW_QCFG": \
- ((x) == 0x32 ? "HWRM_QUEUE_CFG": \
- ((x) == 0x33 ? "HWRM_QUEUE_BUFFERS_QCFG": \
- ((x) == 0x30 ? "HWRM_QUEUE_QPORTCFG": \
- ((x) == 0x31 ? "HWRM_QUEUE_QCFG": \
- ((x) == 0x36 ? "HWRM_QUEUE_PFCENABLE_CFG": \
- ((x) == 0x37 ? "HWRM_QUEUE_PRI2COS_QCFG": \
- ((x) == 0x34 ? "HWRM_QUEUE_BUFFERS_CFG": \
- ((x) == 0x35 ? "HWRM_QUEUE_PFCENABLE_QCFG": \
- ((x) == 0xff14 ? "HWRM_DBG_DUMP": \
- ((x) == 0xff12 ? "HWRM_DBG_WRITE_DIRECT": \
- ((x) == 0xff13 ? "HWRM_DBG_WRITE_INDIRECT": \
- ((x) == 0xff10 ? "HWRM_DBG_READ_DIRECT": \
- ((x) == 0xff11 ? "HWRM_DBG_READ_INDIRECT": \
- ((x) == 0x25 ? "HWRM_PORT_CLR_STATS": \
- ((x) == 0x24 ? "HWRM_PORT_LPBK_QSTATS": \
- ((x) == 0x27 ? "HWRM_PORT_PHY_QCFG": \
- ((x) == 0x26 ? "HWRM_PORT_LPBK_CLR_STATS": \
- ((x) == 0x21 ? "HWRM_PORT_MAC_CFG": \
- ((x) == 0x20 ? "HWRM_PORT_PHY_CFG": \
- ((x) == 0x23 ? "HWRM_PORT_QSTATS": \
- ((x) == 0x22 ? "HWRM_PORT_TS_QUERY": \
- ((x) == 0x29 ? "HWRM_PORT_BLINK_LED": \
- ((x) == 0x28 ? "HWRM_PORT_MAC_QCFG": \
- ((x) == 0x3a ? "HWRM_QUEUE_COS2BW_CFG": \
- "Unknown req_type"))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))
+/* PSN Search Structure (8 bytes) */
-/* Command numbering (8 bytes) */
+struct sq_psn_search {
+ uint32_t opcode_start_psn;
+ /* The opcodes are software defined. */
+ /* Start PSN. */
+ #define SQ_PSN_SEARCH_START_PSN_MASK UINT32_C(0xffffff)
+ #define SQ_PSN_SEARCH_START_PSN_SFT 0
+ /* The opcodes are software defined. */
+ #define SQ_PSN_SEARCH_OPCODE_MASK UINT32_C(0xff000000)
+ #define SQ_PSN_SEARCH_OPCODE_SFT 24
+ uint32_t flags_next_psn;
+ /* Opcode specific flags. */
+ /* Next PSN. Equal to the start PSN of the next WQE. */
+ #define SQ_PSN_SEARCH_NEXT_PSN_MASK UINT32_C(0xffffff)
+ #define SQ_PSN_SEARCH_NEXT_PSN_SFT 0
+ /* Opcode specific flags. */
+ #define SQ_PSN_SEARCH_FLAGS_MASK UINT32_C(0xff000000)
+ #define SQ_PSN_SEARCH_FLAGS_SFT 24
+} __attribute__((packed));
-struct cmd_nums {
- uint16_t req_type;
+/* Send SQ WQE (40 bytes) */
+
+struct sq_send {
+ uint8_t wqe_type;
+ /* This field defines the type of SQ WQE. */
+ /* Send */
+ #define SQ_SEND_WQE_TYPE_SEND UINT32_C(0x0)
/*
- * This version of the specification defines the commands listed in the
- * table below. The following are general implementation requirements
- * for these commands: # All commands listed below that are marked
- * neither reserved nor experimental shall be implemented by the HWRM. #
- * A HWRM client compliant to this specification should not use commands
- * outside of the list below. # A HWRM client compliant to this
- * specification should not use command numbers marked reserved below. #
- * A command marked experimental below may not be implemented by the
- * HWRM. # A command marked experimental may change in the future
- * version of the HWRM specification. # A command not listed below may
- * be implemented by the HWRM. The behavior of commands that are not
- * listed below is outside the scope of this specification.
+ * Send with Immediate Allowed only on reliable connection (RC)
+ * and unreliable datagram (UD) SQ's.
*/
- #define HWRM_VER_GET (UINT32_C(0x0))
- #define HWRM_FUNC_BUF_UNRGTR (UINT32_C(0xe))
- /* Experimental */
- #define HWRM_FUNC_VF_CFG (UINT32_C(0xf))
- /* Reserved for future use */
- #define RESERVED1 (UINT32_C(0x10))
- #define HWRM_FUNC_RESET (UINT32_C(0x11))
- #define HWRM_FUNC_GETFID (UINT32_C(0x12))
- #define HWRM_FUNC_VF_ALLOC (UINT32_C(0x13))
- #define HWRM_FUNC_VF_FREE (UINT32_C(0x14))
- #define HWRM_FUNC_QCAPS (UINT32_C(0x15))
- #define HWRM_FUNC_QCFG (UINT32_C(0x16))
- #define HWRM_FUNC_CFG (UINT32_C(0x17))
- #define HWRM_FUNC_QSTATS (UINT32_C(0x18))
- #define HWRM_FUNC_CLR_STATS (UINT32_C(0x19))
- #define HWRM_FUNC_DRV_UNRGTR (UINT32_C(0x1a))
- #define HWRM_FUNC_VF_RESC_FREE (UINT32_C(0x1b))
- #define HWRM_FUNC_VF_VNIC_IDS_QUERY (UINT32_C(0x1c))
- #define HWRM_FUNC_DRV_RGTR (UINT32_C(0x1d))
- #define HWRM_FUNC_DRV_QVER (UINT32_C(0x1e))
- #define HWRM_FUNC_BUF_RGTR (UINT32_C(0x1f))
- #define HWRM_PORT_PHY_CFG (UINT32_C(0x20))
- #define HWRM_PORT_MAC_CFG (UINT32_C(0x21))
- /* Experimental */
- #define HWRM_PORT_TS_QUERY (UINT32_C(0x22))
- #define HWRM_PORT_QSTATS (UINT32_C(0x23))
- #define HWRM_PORT_LPBK_QSTATS (UINT32_C(0x24))
- /* Experimental */
- #define HWRM_PORT_CLR_STATS (UINT32_C(0x25))
- /* Experimental */
- #define HWRM_PORT_LPBK_CLR_STATS (UINT32_C(0x26))
- #define HWRM_PORT_PHY_QCFG (UINT32_C(0x27))
- /* Experimental */
- #define HWRM_PORT_MAC_QCFG (UINT32_C(0x28))
- /* Experimental */
- #define HWRM_PORT_BLINK_LED (UINT32_C(0x29))
- /* Experimental */
- #define HWRM_PORT_PHY_QCAPS (UINT32_C(0x2a))
- /* Experimental */
- #define HWRM_PORT_PHY_I2C_WRITE (UINT32_C(0x2b))
- /* Experimental */
- #define HWRM_PORT_PHY_I2C_READ (UINT32_C(0x2c))
- #define HWRM_QUEUE_QPORTCFG (UINT32_C(0x30))
- #define HWRM_QUEUE_QCFG (UINT32_C(0x31))
- #define HWRM_QUEUE_CFG (UINT32_C(0x32))
- #define HWRM_QUEUE_BUFFERS_QCFG (UINT32_C(0x33))
- #define HWRM_QUEUE_BUFFERS_CFG (UINT32_C(0x34))
- /* Experimental */
- #define HWRM_QUEUE_PFCENABLE_QCFG (UINT32_C(0x35))
- /* Experimental */
- #define HWRM_QUEUE_PFCENABLE_CFG (UINT32_C(0x36))
- /* Experimental */
- #define HWRM_QUEUE_PRI2COS_QCFG (UINT32_C(0x37))
- /* Experimental */
- #define HWRM_QUEUE_PRI2COS_CFG (UINT32_C(0x38))
- /* Experimental */
- #define HWRM_QUEUE_COS2BW_QCFG (UINT32_C(0x39))
- /* Experimental */
- #define HWRM_QUEUE_COS2BW_CFG (UINT32_C(0x3a))
- #define HWRM_VNIC_ALLOC (UINT32_C(0x40))
- #define HWRM_VNIC_FREE (UINT32_C(0x41))
- #define HWRM_VNIC_CFG (UINT32_C(0x42))
- /* Experimental */
- #define HWRM_VNIC_QCFG (UINT32_C(0x43))
- #define HWRM_VNIC_TPA_CFG (UINT32_C(0x44))
- /* Experimental */
- #define HWRM_VNIC_TPA_QCFG (UINT32_C(0x45))
- #define HWRM_VNIC_RSS_CFG (UINT32_C(0x46))
- #define HWRM_VNIC_RSS_QCFG (UINT32_C(0x47))
- #define HWRM_VNIC_PLCMODES_CFG (UINT32_C(0x48))
- #define HWRM_VNIC_PLCMODES_QCFG (UINT32_C(0x49))
- /* Experimental */
- #define HWRM_VNIC_QCAPS (UINT32_C(0x4a))
- #define HWRM_RING_ALLOC (UINT32_C(0x50))
- #define HWRM_RING_FREE (UINT32_C(0x51))
- #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (UINT32_C(0x52))
- #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (UINT32_C(0x53))
- #define HWRM_RING_RESET (UINT32_C(0x5e))
- #define HWRM_RING_GRP_ALLOC (UINT32_C(0x60))
- #define HWRM_RING_GRP_FREE (UINT32_C(0x61))
- #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (UINT32_C(0x70))
- #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (UINT32_C(0x71))
- #define HWRM_CFA_L2_FILTER_ALLOC (UINT32_C(0x90))
- #define HWRM_CFA_L2_FILTER_FREE (UINT32_C(0x91))
- #define HWRM_CFA_L2_FILTER_CFG (UINT32_C(0x92))
- #define HWRM_CFA_L2_SET_RX_MASK (UINT32_C(0x93))
- /* Reserved for future use */
- #define RESERVED3 (UINT32_C(0x94))
- #define HWRM_CFA_TUNNEL_FILTER_ALLOC (UINT32_C(0x95))
- #define HWRM_CFA_TUNNEL_FILTER_FREE (UINT32_C(0x96))
- /* Experimental */
- #define HWRM_CFA_ENCAP_RECORD_ALLOC (UINT32_C(0x97))
- /* Experimental */
- #define HWRM_CFA_ENCAP_RECORD_FREE (UINT32_C(0x98))
- #define HWRM_CFA_NTUPLE_FILTER_ALLOC (UINT32_C(0x99))
- #define HWRM_CFA_NTUPLE_FILTER_FREE (UINT32_C(0x9a))
- #define HWRM_CFA_NTUPLE_FILTER_CFG (UINT32_C(0x9b))
- /* Experimental */
- #define HWRM_CFA_EM_FLOW_ALLOC (UINT32_C(0x9c))
- /* Experimental */
- #define HWRM_CFA_EM_FLOW_FREE (UINT32_C(0x9d))
- /* Experimental */
- #define HWRM_CFA_EM_FLOW_CFG (UINT32_C(0x9e))
- #define HWRM_TUNNEL_DST_PORT_QUERY (UINT32_C(0xa0))
- #define HWRM_TUNNEL_DST_PORT_ALLOC (UINT32_C(0xa1))
- #define HWRM_TUNNEL_DST_PORT_FREE (UINT32_C(0xa2))
- #define HWRM_STAT_CTX_ALLOC (UINT32_C(0xb0))
- #define HWRM_STAT_CTX_FREE (UINT32_C(0xb1))
- #define HWRM_STAT_CTX_QUERY (UINT32_C(0xb2))
- #define HWRM_STAT_CTX_CLR_STATS (UINT32_C(0xb3))
- #define HWRM_FW_RESET (UINT32_C(0xc0))
- #define HWRM_FW_QSTATUS (UINT32_C(0xc1))
- /* Experimental */
- #define HWRM_FW_SET_TIME (UINT32_C(0xc8))
- /* Experimental */
- #define HWRM_FW_GET_TIME (UINT32_C(0xc9))
- #define HWRM_EXEC_FWD_RESP (UINT32_C(0xd0))
- #define HWRM_REJECT_FWD_RESP (UINT32_C(0xd1))
- #define HWRM_FWD_RESP (UINT32_C(0xd2))
- #define HWRM_FWD_ASYNC_EVENT_CMPL (UINT32_C(0xd3))
- #define HWRM_TEMP_MONITOR_QUERY (UINT32_C(0xe0))
- /* Experimental */
- #define HWRM_WOL_FILTER_ALLOC (UINT32_C(0xf0))
- /* Experimental */
- #define HWRM_WOL_FILTER_FREE (UINT32_C(0xf1))
- /* Experimental */
- #define HWRM_WOL_FILTER_QCFG (UINT32_C(0xf2))
- /* Experimental */
- #define HWRM_WOL_REASON_QCFG (UINT32_C(0xf3))
- /* Experimental */
- #define HWRM_DBG_READ_DIRECT (UINT32_C(0xff10))
- /* Experimental */
- #define HWRM_DBG_READ_INDIRECT (UINT32_C(0xff11))
- /* Experimental */
- #define HWRM_DBG_WRITE_DIRECT (UINT32_C(0xff12))
- /* Experimental */
- #define HWRM_DBG_WRITE_INDIRECT (UINT32_C(0xff13))
- #define HWRM_DBG_DUMP (UINT32_C(0xff14))
- #define HWRM_NVM_INSTALL_UPDATE (UINT32_C(0xfff3))
- #define HWRM_NVM_MODIFY (UINT32_C(0xfff4))
- #define HWRM_NVM_VERIFY_UPDATE (UINT32_C(0xfff5))
- #define HWRM_NVM_GET_DEV_INFO (UINT32_C(0xfff6))
- #define HWRM_NVM_ERASE_DIR_ENTRY (UINT32_C(0xfff7))
- #define HWRM_NVM_MOD_DIR_ENTRY (UINT32_C(0xfff8))
- #define HWRM_NVM_FIND_DIR_ENTRY (UINT32_C(0xfff9))
- #define HWRM_NVM_GET_DIR_ENTRIES (UINT32_C(0xfffa))
- #define HWRM_NVM_GET_DIR_INFO (UINT32_C(0xfffb))
- #define HWRM_NVM_RAW_DUMP (UINT32_C(0xfffc))
- #define HWRM_NVM_READ (UINT32_C(0xfffd))
- #define HWRM_NVM_WRITE (UINT32_C(0xfffe))
- #define HWRM_NVM_RAW_WRITE_BLK (UINT32_C(0xffff))
- uint16_t unused_0[3];
+ #define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD UINT32_C(0x1)
+ /*
+ * Send with Invalidate. Allowed only on reliable connection
+ * (RC) SQ's.
+ */
+ #define SQ_SEND_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2)
+ uint8_t flags;
+ /*
+ * Set if completion signaling is requested. If this bit is 0, and the
+ * SQ is configured to support Unsignaled completion the controller
+ * should not generate a CQE unless there was an error. This refers to
+ * the CQE on the sender side. (The se flag refers to the receiver
+ * side).
+ */
+ #define SQ_SEND_FLAGS_SIGNAL_COMP UINT32_C(0x1)
+ /*
+ * Indication to complete all previous RDMA Read or Atomic WQEs on the
+ * SQ before executing this WQE. This flag must be zero for a UD send.
+ */
+ #define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
+ /*
+ * For local invalidate request. Indicate to complete all previous SQ's
+ * WQEs before executing this WQE. This flag must be zero for a UD send.
+ */
+ #define SQ_SEND_FLAGS_UC_FENCE UINT32_C(0x4)
+ /*
+ * Solicit event flag. Indication sent in BTH header to the receiver to
+ * generate a Completion Event Notification, i.e. CNQE. This bit should
+ * be set only in the last (or only) packet of the message.
+ */
+ #define SQ_SEND_FLAGS_SE UINT32_C(0x8)
+ /*
+ * Indicate that inline data is posted to the SQ in the data area of
+ * this WQE.
+ */
+ #define SQ_SEND_FLAGS_INLINE UINT32_C(0x10)
+ uint8_t wqe_size;
+ /*
+ * The number of 16 bytes chunks of data including this first word of
+ * the request that are a valid part of the request. The valid 16 bytes
+ * units other than the WQE structure can be SGEs (Scatter Gather
+ * Elements) OR inline data. While this field defines the valid WQE
+ * size. The actual total WQE size is always 128B.
+ */
+ uint8_t reserved8_1;
+ uint32_t inv_key_or_imm_data;
+ /*
+ * Either invalidate key (R_Key of the remote host) that will be send
+ * with IETH (Invalidate ETH) if wqe_type is of Send with Invalidate, or
+ * immediate value that will be sent with ImmDt header if wqe_type is
+ * Send with Immediate.
+ */
+ uint32_t length;
+ /* This field represents a 32-bit total data length, in bytes. */
+ uint32_t q_key;
+ /*
+ * When in the SQ of a UD QP, indicates the q_key to be used in the
+ * transmitted packet. However, if the most significant bit of this
+ * field is set, then the q_key will be taken from QP context, rather
+ * than from this field. When in the SQ of a non-UD QP, this field is
+ * reserved and should be filled with zeros.
+ */
+ uint32_t dst_qp;
+ /*
+ * When in the SQ of a UD QP, indicates the destination QP to be used in
+ * the transmitted packet. When in the SQ of a non-UD QP, this field is
+ * reserved and should be filled with zeros.
+ */
+ #define SQ_SEND_DST_QP_MASK UINT32_C(0xffffff)
+ #define SQ_SEND_DST_QP_SFT 0
+ #define SQ_SEND_RESERVED8_2_MASK UINT32_C(0xff000000)
+ #define SQ_SEND_RESERVED8_2_SFT 24
+ uint32_t avid;
+ /* This field is reserved for future expansion of the AVID. */
+ /*
+ * If the serv_type is 'UD', then this field supplies the AVID (Address
+ * Vector ID).
+ */
+ #define SQ_SEND_AVID_MASK UINT32_C(0xfffff)
+ #define SQ_SEND_AVID_SFT 0
+ /* This field is reserved for future expansion of the AVID. */
+ #define SQ_SEND_RESERVED_AVID_MASK UINT32_C(0xfff00000)
+ #define SQ_SEND_RESERVED_AVID_SFT 20
+ uint64_t reserved64;
+ uint32_t data[24];
+ /*
+ * When inline=0, then this area is filled with from 1 to 6 SGEs based
+ * on the wqe_size field. When inline=1, this area is filled with
+ * payload data for the send based on the length_or_AVID field. Bits
+ * [7:0] of word 0 hold the first byte to go out on the wire.
+ */
} __attribute__((packed));
-#define GET_HWRM_ERROR_CODE(x) \
- ((x) == 0xf ? "HWRM_ERROR": \
- ((x) == 0xffff ? "CMD_NOT_SUPPORTED": \
- ((x) == 0xfffe ? "UNKNOWN_ERR": \
- ((x) == 0x4 ? "RESOURCE_ALLOC_ERROR": \
- ((x) == 0x5 ? "INVALID_FLAGS": \
- ((x) == 0x6 ? "INVALID_ENABLES": \
- ((x) == 0x0 ? "SUCCESS": \
- ((x) == 0x1 ? "FAIL": \
- ((x) == 0x2 ? "INVALID_PARAMS": \
- ((x) == 0x3 ? "RESOURCE_ACCESS_DENIED": \
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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