svn commit: r324563 - head/sys/arm/allwinner

[Emmanuel Vadot]

Author: manu
Date: Thu Oct 12 18:00:29 2017
New Revision: 324563
URL: https://svnweb.freebsd.org/changeset/base/324563

Log:
  a10_ehci: Remove the passby code
  
  It doesn't seems to be needed anymore and this make ehci working again
  on the Pine64.
  Thanks to jmcneill@ for the help.
  
  Tested on:	Pine64 (A64), OrangePi One (H3), BananapiM2 (A31s)

Modified:
  head/sys/arm/allwinner/a10_ehci.c

Modified: head/sys/arm/allwinner/a10_ehci.c
==============================================================================
--- head/sys/arm/allwinner/a10_ehci.c	Thu Oct 12 15:53:54 2017	(r324562)
+++ head/sys/arm/allwinner/a10_ehci.c	Thu Oct 12 18:00:29 2017	(r324563)
@@ -65,17 +65,10 @@ __FBSDID("$FreeBSD$");
 
 #define EHCI_HC_DEVSTR			"Allwinner Integrated USB 2.0 controller"
 
-#define SW_USB_PMU_IRQ_ENABLE		0x800
-
 #define SW_SDRAM_REG_HPCR_USB1		(0x250 + ((1 << 2) * 4))
 #define SW_SDRAM_REG_HPCR_USB2		(0x250 + ((1 << 2) * 5))
 #define SW_SDRAM_BP_HPCR_ACCESS		(1 << 0)
 
-#define SW_ULPI_BYPASS			(1 << 0)
-#define SW_AHB_INCRX_ALIGN		(1 << 8)
-#define SW_AHB_INCR4			(1 << 9)
-#define SW_AHB_INCR8			(1 << 10)
-
 #define	USB_CONF(d)			\
 	(void *)ofw_bus_search_compatible((d), compat_data)->ocd_data
 
@@ -124,7 +117,7 @@ static struct ofw_compat_data compat_data[] = {
 	{ "allwinner,sun7i-a20-ehci",	(uintptr_t)&a10_ehci_conf },
 	{ "allwinner,sun8i-a83t-ehci",	(uintptr_t)&a31_ehci_conf },
 	{ "allwinner,sun8i-h3-ehci",	(uintptr_t)&a31_ehci_conf },
-	/* { "allwinner,sun50i-a64-ehci",	(uintptr_t)&a31_ehci_conf }, */
+	{ "allwinner,sun50i-a64-ehci",	(uintptr_t)&a31_ehci_conf },
 	{ NULL,				(uintptr_t)NULL }
 };
 
@@ -254,14 +247,6 @@ a10_ehci_attach(device_t self)
 		}
 	}
 
-	/* Enable passby */
-	reg_value = A10_READ_4(sc, SW_USB_PMU_IRQ_ENABLE);
-	reg_value |= SW_AHB_INCR8; /* AHB INCR8 enable */
-	reg_value |= SW_AHB_INCR4; /* AHB burst type INCR4 enable */
-	reg_value |= SW_AHB_INCRX_ALIGN; /* AHB INCRX align enable */
-	reg_value |= SW_ULPI_BYPASS; /* ULPI bypass enable */
-	A10_WRITE_4(sc, SW_USB_PMU_IRQ_ENABLE, reg_value);
-
 	/* Configure port */
 	if (conf->sdram_init) {
 		reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2);
@@ -332,14 +317,6 @@ a10_ehci_detach(device_t self)
 		reg_value &= ~SW_SDRAM_BP_HPCR_ACCESS;
 		A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value);
 	}
-
-	/* Disable passby */
-	reg_value = A10_READ_4(sc, SW_USB_PMU_IRQ_ENABLE);
-	reg_value &= ~SW_AHB_INCR8; /* AHB INCR8 disable */
-	reg_value &= ~SW_AHB_INCR4; /* AHB burst type INCR4 disable */
-	reg_value &= ~SW_AHB_INCRX_ALIGN; /* AHB INCRX align disable */
-	reg_value &= ~SW_ULPI_BYPASS; /* ULPI bypass disable */
-	A10_WRITE_4(sc, SW_USB_PMU_IRQ_ENABLE, reg_value);
 
 	/* Disable clock */
 	TAILQ_FOREACH_SAFE(clk, &aw_sc->clk_list, next, clk_tmp) {