svn commit: r326230 - in head/sys/arm64: arm64 include
Ed Schouten
ed at FreeBSD.org
Sun Nov 26 14:56:25 UTC 2017
Author: ed
Date: Sun Nov 26 14:56:23 2017
New Revision: 326230
URL: https://svnweb.freebsd.org/changeset/base/326230
Log:
Add a Saved Process Status Register bit for AArch32 execution mode.
The documentation on the Saved Process Status Register (SPSR) is a bit
weird; the M[4] bit is documented separately from M[3:0]. The M[4] bit
can be toggled to switch to 32-bit execution mode. This functionality is
orthogonal to M[3:0].
Change the definition of PSR_M_MASK to no longer include M[4]. Add a new
definition, PSR_AARCH32 that can be used to toggle 32-bit independently.
This bit will be used by the cloudabi32 code to force execution of
userspace code in 32-bit mode.
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D13148
Modified:
head/sys/arm64/arm64/machdep.c
head/sys/arm64/include/armreg.h
Modified: head/sys/arm64/arm64/machdep.c
==============================================================================
--- head/sys/arm64/arm64/machdep.c Sun Nov 26 14:53:56 2017 (r326229)
+++ head/sys/arm64/arm64/machdep.c Sun Nov 26 14:56:23 2017 (r326230)
@@ -405,7 +405,7 @@ set_mcontext(struct thread *td, mcontext_t *mcp)
spsr = mcp->mc_gpregs.gp_spsr;
if ((spsr & PSR_M_MASK) != PSR_M_EL0t ||
- (spsr & (PSR_F | PSR_I | PSR_A | PSR_D)) != 0)
+ (spsr & (PSR_AARCH32 | PSR_F | PSR_I | PSR_A | PSR_D)) != 0)
return (EINVAL);
memcpy(tf->tf_x, mcp->mc_gpregs.gp_x, sizeof(tf->tf_x));
Modified: head/sys/arm64/include/armreg.h
==============================================================================
--- head/sys/arm64/include/armreg.h Sun Nov 26 14:53:56 2017 (r326229)
+++ head/sys/arm64/include/armreg.h Sun Nov 26 14:56:23 2017 (r326230)
@@ -549,7 +549,6 @@
/* SPSR_EL1 */
/*
* When the exception is taken in AArch64:
- * M[4] is 0 for AArch64 mode
* M[3:2] is the exception level
* M[1] is unused
* M[0] is the SP select:
@@ -561,8 +560,9 @@
#define PSR_M_EL1h 0x00000005
#define PSR_M_EL2t 0x00000008
#define PSR_M_EL2h 0x00000009
-#define PSR_M_MASK 0x0000001f
+#define PSR_M_MASK 0x0000000f
+#define PSR_AARCH32 0x00000010
#define PSR_F 0x00000040
#define PSR_I 0x00000080
#define PSR_A 0x00000100
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