svn commit: r319255 - stable/10/contrib/ofed/libcxgb4/src
Navdeep Parhar
np at FreeBSD.org
Tue May 30 21:57:30 UTC 2017
Author: np
Date: Tue May 30 21:57:25 2017
New Revision: 319255
URL: https://svnweb.freebsd.org/changeset/base/319255
Log:
MFC r314176 and r318973.
r314176:
Add support for RDMA from userspace with T6 cards.
r318973:
libcxgb4: Use memcpy instead of copying WRs 8B at a time in the userspace
RDMA library for cxgbe(4).
Sponsored by: Chelsio Communications
Modified:
stable/10/contrib/ofed/libcxgb4/src/dev.c
stable/10/contrib/ofed/libcxgb4/src/qp.c
stable/10/contrib/ofed/libcxgb4/src/t4.h
stable/10/contrib/ofed/libcxgb4/src/t4_chip_type.h
stable/10/contrib/ofed/libcxgb4/src/t4_pci_id_tbl.h
stable/10/contrib/ofed/libcxgb4/src/t4_regs.h
stable/10/contrib/ofed/libcxgb4/src/verbs.c
Directory Properties:
stable/10/ (props changed)
Modified: stable/10/contrib/ofed/libcxgb4/src/dev.c
==============================================================================
--- stable/10/contrib/ofed/libcxgb4/src/dev.c Tue May 30 21:55:48 2017 (r319254)
+++ stable/10/contrib/ofed/libcxgb4/src/dev.c Tue May 30 21:57:25 2017 (r319255)
@@ -145,10 +145,10 @@ static struct ibv_context *c4iw_alloc_context(struct i
context->ibv_ctx.ops = c4iw_ctx_ops;
switch (rhp->chip_version) {
+ case CHELSIO_T6:
case CHELSIO_T5:
- PDBG("%s T5/T4 device\n", __FUNCTION__);
case CHELSIO_T4:
- PDBG("%s T4 device\n", __FUNCTION__);
+ PDBG("%s T%d device\n", __FUNCTION__, rhp->chip_version);
context->ibv_ctx.ops.async_event = c4iw_async_event;
context->ibv_ctx.ops.post_send = c4iw_post_send;
context->ibv_ctx.ops.post_recv = c4iw_post_receive;
@@ -390,29 +390,26 @@ static struct ibv_device *cxgb4_driver_init(const char
int abi_version)
{
char devstr[IBV_SYSFS_PATH_MAX], ibdev[16], value[128], *cp;
- char t5nexstr[IBV_SYSFS_PATH_MAX];
+ char dev_str[IBV_SYSFS_PATH_MAX];
struct c4iw_dev *dev;
unsigned vendor, device, fw_maj, fw_min;
int i;
- char devnum=0;
+ char devnum;
char ib_param[16];
#ifndef __linux__
if (ibv_read_sysfs_file(uverbs_sys_path, "ibdev",
ibdev, sizeof ibdev) < 0)
return NULL;
- /*
- * Extract the non-numeric part of ibdev
- * say "t5nex0" -> devname=="t5nex", devnum=0
- */
- if (strstr(ibdev,"t5nex")) {
- devnum = atoi(ibdev+strlen("t5nex"));
- sprintf(t5nexstr, "/dev/t5nex/%d", devnum);
+
+ if (ibdev[0] == 't' && ibdev[1] >= '4' && ibdev[1] <= '6' &&
+ strstr(&ibdev[2], "nex") && (devnum = atoi(&ibdev[5])) >= 0) {
+ snprintf(dev_str, sizeof(dev_str), "/dev/t%cnex/%d", ibdev[1],
+ devnum);
} else
return NULL;
- if (ibv_read_sysfs_file(t5nexstr, "\%pnpinfo",
- value, sizeof value) < 0)
+ if (ibv_read_sysfs_file(dev_str, "\%pnpinfo", value, sizeof value) < 0)
return NULL;
else {
if (strstr(value,"vendor=")) {
@@ -449,7 +446,7 @@ found:
#ifndef __linux__
- if (ibv_read_sysfs_file(t5nexstr, "firmware_version",
+ if (ibv_read_sysfs_file(dev_str, "firmware_version",
value, sizeof value) < 0)
return NULL;
#else
Modified: stable/10/contrib/ofed/libcxgb4/src/qp.c
==============================================================================
--- stable/10/contrib/ofed/libcxgb4/src/qp.c Tue May 30 21:55:48 2017 (r319254)
+++ stable/10/contrib/ofed/libcxgb4/src/qp.c Tue May 30 21:57:25 2017 (r319255)
@@ -47,39 +47,49 @@ struct c4iw_stats c4iw_stats;
static void copy_wr_to_sq(struct t4_wq *wq, union t4_wr *wqe, u8 len16)
{
- u64 *src, *dst;
+ void *src, *dst;
+ uintptr_t end;
+ int total, len;
- src = (u64 *)wqe;
- dst = (u64 *)((u8 *)wq->sq.queue + wq->sq.wq_pidx * T4_EQ_ENTRY_SIZE);
+ src = &wqe->flits[0];
+ dst = &wq->sq.queue->flits[wq->sq.wq_pidx *
+ (T4_EQ_ENTRY_SIZE / sizeof(__be64))];
if (t4_sq_onchip(wq)) {
len16 = align(len16, 4);
wc_wmb();
}
- while (len16) {
- *dst++ = *src++;
- if (dst == (u64 *)&wq->sq.queue[wq->sq.size])
- dst = (u64 *)wq->sq.queue;
- *dst++ = *src++;
- if (dst == (u64 *)&wq->sq.queue[wq->sq.size])
- dst = (u64 *)wq->sq.queue;
- len16--;
+
+ total = len16 * 16;
+ end = (uintptr_t)&wq->sq.queue[wq->sq.size];
+ if (__predict_true((uintptr_t)dst + total <= end)) {
+ /* Won't wrap around. */
+ memcpy(dst, src, total);
+ } else {
+ len = end - (uintptr_t)dst;
+ memcpy(dst, src, len);
+ memcpy(wq->sq.queue, src + len, total - len);
}
}
static void copy_wr_to_rq(struct t4_wq *wq, union t4_recv_wr *wqe, u8 len16)
{
- u64 *src, *dst;
+ void *src, *dst;
+ uintptr_t end;
+ int total, len;
- src = (u64 *)wqe;
- dst = (u64 *)((u8 *)wq->rq.queue + wq->rq.wq_pidx * T4_EQ_ENTRY_SIZE);
- while (len16) {
- *dst++ = *src++;
- if (dst >= (u64 *)&wq->rq.queue[wq->rq.size])
- dst = (u64 *)wq->rq.queue;
- *dst++ = *src++;
- if (dst >= (u64 *)&wq->rq.queue[wq->rq.size])
- dst = (u64 *)wq->rq.queue;
- len16--;
+ src = &wqe->flits[0];
+ dst = &wq->rq.queue->flits[wq->rq.wq_pidx *
+ (T4_EQ_ENTRY_SIZE / sizeof(__be64))];
+
+ total = len16 * 16;
+ end = (uintptr_t)&wq->rq.queue[wq->rq.size];
+ if (__predict_true((uintptr_t)dst + total <= end)) {
+ /* Won't wrap around. */
+ memcpy(dst, src, total);
+ } else {
+ len = end - (uintptr_t)dst;
+ memcpy(dst, src, len);
+ memcpy(wq->rq.queue, src + len, total - len);
}
}
@@ -393,7 +403,7 @@ int c4iw_post_send(struct ibv_qp *ibqp, struct ibv_sen
idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
}
- t4_ring_sq_db(&qhp->wq, idx, dev_is_t5(qhp->rhp),
+ t4_ring_sq_db(&qhp->wq, idx, dev_is_t4(qhp->rhp),
len16, wqe);
qhp->wq.sq.queue[qhp->wq.sq.size].status.host_wq_pidx = \
(qhp->wq.sq.wq_pidx);
@@ -457,7 +467,7 @@ int c4iw_post_receive(struct ibv_qp *ibqp, struct ibv_
num_wrs--;
}
- t4_ring_rq_db(&qhp->wq, idx, dev_is_t5(qhp->rhp),
+ t4_ring_rq_db(&qhp->wq, idx, dev_is_t4(qhp->rhp),
len16, wqe);
qhp->wq.rq.queue[qhp->wq.rq.size].status.host_wq_pidx = \
(qhp->wq.rq.wq_pidx);
Modified: stable/10/contrib/ofed/libcxgb4/src/t4.h
==============================================================================
--- stable/10/contrib/ofed/libcxgb4/src/t4.h Tue May 30 21:55:48 2017 (r319254)
+++ stable/10/contrib/ofed/libcxgb4/src/t4.h Tue May 30 21:57:25 2017 (r319255)
@@ -484,11 +484,11 @@ static void copy_wqe_to_udb(volatile u32 *udb_offset,
extern int ma_wr;
extern int t5_en_wc;
-static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5, u8 len16,
+static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t4, u8 len16,
union t4_wr *wqe)
{
wc_wmb();
- if (t5) {
+ if (!t4) {
if (t5_en_wc && inc == 1 && wq->sq.wc_reg_available) {
PDBG("%s: WC wq->sq.pidx = %d; len16=%d\n",
__func__, wq->sq.pidx, len16);
@@ -517,11 +517,11 @@ static inline void t4_ring_sq_db(struct t4_wq *wq, u16
writel(V_QID(wq->sq.qid & wq->qid_mask) | V_PIDX(inc), wq->sq.udb);
}
-static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5, u8 len16,
+static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t4, u8 len16,
union t4_recv_wr *wqe)
{
wc_wmb();
- if (t5) {
+ if (!t4) {
if (t5_en_wc && inc == 1 && wq->sq.wc_reg_available) {
PDBG("%s: WC wq->rq.pidx = %d; len16=%d\n",
__func__, wq->rq.pidx, len16);
Modified: stable/10/contrib/ofed/libcxgb4/src/t4_chip_type.h
==============================================================================
--- stable/10/contrib/ofed/libcxgb4/src/t4_chip_type.h Tue May 30 21:55:48 2017 (r319254)
+++ stable/10/contrib/ofed/libcxgb4/src/t4_chip_type.h Tue May 30 21:57:25 2017 (r319255)
@@ -1,7 +1,7 @@
/*
- * This file is part of the Chelsio T4 Ethernet driver.
+ * This file is part of the Chelsio T4/T5/T6 Ethernet driver.
*
- * Copyright (C) 2003-2014 Chelsio Communications. All rights reserved.
+ * Copyright (C) 2003-2016 Chelsio Communications. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
@@ -30,6 +30,8 @@
#define CHELSIO_T4_FPGA 0xa
#define CHELSIO_T5 0x5
#define CHELSIO_T5_FPGA 0xb
+#define CHELSIO_T6 0x6
+#define CHELSIO_T6_FPGA 0xc
/*
* Translate a PCI Device ID to a base Chelsio Chip Version -- CHELSIO_T4,
@@ -43,12 +45,26 @@
* Finally: This will of course need to be expanded as future chips are
* developed.
*/
-#define CHELSIO_PCI_ID_CHIP_VERSION(__DeviceID) \
- (CHELSIO_PCI_ID_VER(__DeviceID) == CHELSIO_T4 || \
- CHELSIO_PCI_ID_VER(__DeviceID) == CHELSIO_T4_FPGA \
- ? CHELSIO_T4 \
- : CHELSIO_T5)
+static inline unsigned int
+CHELSIO_PCI_ID_CHIP_VERSION(unsigned int DeviceID)
+{
+ switch (CHELSIO_PCI_ID_VER(DeviceID)) {
+ case CHELSIO_T4:
+ case CHELSIO_T4_FPGA:
+ return CHELSIO_T4;
+ case CHELSIO_T5:
+ case CHELSIO_T5_FPGA:
+ return CHELSIO_T5;
+
+ case CHELSIO_T6:
+ case CHELSIO_T6_FPGA:
+ return CHELSIO_T6;
+ }
+
+ return 0;
+}
+
/*
* Internally we code the Chelsio T4 Family "Chip Code" as a tuple:
*
@@ -72,9 +88,13 @@ enum chip_type {
T4_LAST_REV = T4_A2,
T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
- T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
+ T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
T5_FIRST_REV = T5_A0,
T5_LAST_REV = T5_A1,
+
+ T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
+ T6_FIRST_REV = T6_A0,
+ T6_LAST_REV = T6_A0,
};
static inline int is_t4(enum chip_type chip)
@@ -86,6 +106,11 @@ static inline int is_t5(enum chip_type chip)
{
return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5);
+}
+
+static inline int is_t6(enum chip_type chip)
+{
+ return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6);
}
static inline int is_fpga(enum chip_type chip)
Modified: stable/10/contrib/ofed/libcxgb4/src/t4_pci_id_tbl.h
==============================================================================
--- stable/10/contrib/ofed/libcxgb4/src/t4_pci_id_tbl.h Tue May 30 21:55:48 2017 (r319254)
+++ stable/10/contrib/ofed/libcxgb4/src/t4_pci_id_tbl.h Tue May 30 21:57:25 2017 (r319255)
@@ -1,7 +1,7 @@
/*
- * This file is part of the Chelsio T4 Ethernet driver.
+ * This file is part of the Chelsio T4/T5/T6 Ethernet driver.
*
- * Copyright (C) 2003-2014 Chelsio Communications. All rights reserved.
+ * Copyright (C) 2003-2017 Chelsio Communications. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
@@ -44,7 +44,6 @@
* -- If defined, indicates that the OS Driver has support for Bypass
* -- Adapters.
*/
-#ifdef CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
/*
* Some sanity checks ...
@@ -96,10 +95,13 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
CH_PCI_ID_TABLE_ENTRY(0xa000), /* PE10K FPGA */
CH_PCI_ID_TABLE_ENTRY(0xb000), /* PF0 T5 PE10K5 FPGA */
CH_PCI_ID_TABLE_ENTRY(0xb001), /* PF0 T5 PE10K FPGA */
+ CH_PCI_ID_TABLE_ENTRY(0xc006), /* PF0 T6 PE10K6 FPGA */
#else
CH_PCI_ID_TABLE_FENTRY(0xa000), /* PE10K FPGA */
CH_PCI_ID_TABLE_FENTRY(0xb000), /* PF0 T5 PE10K5 FPGA */
CH_PCI_ID_TABLE_FENTRY(0xb001), /* PF0 T5 PE10K FPGA */
+ CH_PCI_ID_TABLE_FENTRY(0xc006), /* PF0 T6 PE10K6 FPGA */
+ CH_PCI_ID_TABLE_FENTRY(0xc106), /* PF1 T6 PE10K6 FPGA */
#endif
/*
@@ -108,6 +110,7 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
#if ((CH_PCI_DEVICE_ID_FUNCTION == 5) || (CH_PCI_DEVICE_ID_FUNCTION == 6))
CH_PCI_ID_TABLE_ENTRY(0xa001), /* PF1 PE10K FPGA FCOE */
CH_PCI_ID_TABLE_ENTRY(0xa002), /* PE10K FPGA iSCSI */
+ CH_PCI_ID_TABLE_ENTRY(0xc106), /* PF1 T6 PE10K6 FPGA */
#endif
/*
@@ -166,10 +169,50 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
CH_PCI_ID_TABLE_FENTRY(0x5013), /* T580-chr */
CH_PCI_ID_TABLE_FENTRY(0x5014), /* T580-so */
CH_PCI_ID_TABLE_FENTRY(0x5015), /* T502-bt */
+ CH_PCI_ID_TABLE_FENTRY(0x5016), /* T580-OCP-SO */
+ CH_PCI_ID_TABLE_FENTRY(0x5017), /* T520-OCP-SO */
+ CH_PCI_ID_TABLE_FENTRY(0x5018), /* T540-BT */
CH_PCI_ID_TABLE_FENTRY(0x5080), /* Custom T540-cr */
CH_PCI_ID_TABLE_FENTRY(0x5081), /* Custom T540-LL-cr */
-CH_PCI_DEVICE_ID_TABLE_DEFINE_END;
+ CH_PCI_ID_TABLE_FENTRY(0x5082), /* Custom T504-cr */
+ CH_PCI_ID_TABLE_FENTRY(0x5083), /* Custom T540-CR */
+ CH_PCI_ID_TABLE_FENTRY(0x5084), /* Custom T580-cr */
+ CH_PCI_ID_TABLE_FENTRY(0x5085), /* Custom 3x T580-CR */
+ CH_PCI_ID_TABLE_FENTRY(0x5086), /* Custom 2x T580-CR */
+ CH_PCI_ID_TABLE_FENTRY(0x5087), /* Custom T580-CR */
+ CH_PCI_ID_TABLE_FENTRY(0x5088), /* Custom T570-CR */
+ CH_PCI_ID_TABLE_FENTRY(0x5089), /* Custom T520-CR */
+ CH_PCI_ID_TABLE_FENTRY(0x5090), /* Custom T540-CR */
+ CH_PCI_ID_TABLE_FENTRY(0x5091), /* Custom T522-CR */
+ CH_PCI_ID_TABLE_FENTRY(0x5092), /* Custom T520-CR */
+ CH_PCI_ID_TABLE_FENTRY(0x5093), /* Custom SECA */
+ CH_PCI_ID_TABLE_FENTRY(0x5094), /* Custom T540-CR */
+ CH_PCI_ID_TABLE_FENTRY(0x5095), /* Custom T540-CR-SO */
+ CH_PCI_ID_TABLE_FENTRY(0x5096), /* Custom T580-CR */
+ CH_PCI_ID_TABLE_FENTRY(0x5097), /* Custom T520-KR */
+ CH_PCI_ID_TABLE_FENTRY(0x5098), /* Custom 2x40G QSFP */
+ CH_PCI_ID_TABLE_FENTRY(0x5099), /* Custom 2x40G QSFP */
+ CH_PCI_ID_TABLE_FENTRY(0x509A), /* Custom T520-CR */
+ CH_PCI_ID_TABLE_FENTRY(0x509B), /* Custom T540-CR LOM */
+ CH_PCI_ID_TABLE_FENTRY(0x509c), /* Custom T520-CR SFP+ LOM */
+ CH_PCI_ID_TABLE_FENTRY(0x509d), /* Custom T540-CR SFP+ */
-#endif /* CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN */
+ /* T6 adapter */
+ CH_PCI_ID_TABLE_FENTRY(0x6000),
+ CH_PCI_ID_TABLE_FENTRY(0x6001),
+ CH_PCI_ID_TABLE_FENTRY(0x6002),
+ CH_PCI_ID_TABLE_FENTRY(0x6003),
+ CH_PCI_ID_TABLE_FENTRY(0x6004),
+ CH_PCI_ID_TABLE_FENTRY(0x6005),
+ CH_PCI_ID_TABLE_FENTRY(0x6006),
+ CH_PCI_ID_TABLE_FENTRY(0x6007),
+ CH_PCI_ID_TABLE_FENTRY(0x6008),
+ CH_PCI_ID_TABLE_FENTRY(0x6009),
+ CH_PCI_ID_TABLE_FENTRY(0x600d),
+ CH_PCI_ID_TABLE_FENTRY(0x6010),
+ CH_PCI_ID_TABLE_FENTRY(0x6011),
+ CH_PCI_ID_TABLE_FENTRY(0x6014),
+ CH_PCI_ID_TABLE_FENTRY(0x6015),
+CH_PCI_DEVICE_ID_TABLE_DEFINE_END;
#endif /* __T4_PCI_ID_TBL_H__ */
Modified: stable/10/contrib/ofed/libcxgb4/src/t4_regs.h
==============================================================================
--- stable/10/contrib/ofed/libcxgb4/src/t4_regs.h Tue May 30 21:55:48 2017 (r319254)
+++ stable/10/contrib/ofed/libcxgb4/src/t4_regs.h Tue May 30 21:57:25 2017 (r319255)
@@ -1,4 +1,8 @@
/* This file is automatically generated --- changes will be lost */
+/* Generation Date : Fri Oct 28 19:22:40 IST 2016 */
+/* Directory name: t4_reg.txt, Changeset: */
+/* Directory name: t5_reg.txt, Changeset: 6938:9111c5bdce6e */
+/* Directory name: t6_reg.txt, Changeset: 4252:437fb8972e44 */
#define MYPF_BASE 0x1b000
#define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
@@ -339,9 +343,141 @@
#define EDC_H_ECC_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define NUM_EDC_H_ECC_ERR_DATA_INSTANCES 16
+#define SGE_DEBUG1_DBP_THREAD(idx) (A_SGE_DEBUG1_DBP_THREAD + (idx) * 4)
+#define NUM_SGE_DEBUG1_DBP_THREAD_INSTANCES 4
+
+#define SGE_DEBUG0_DBP_THREAD(idx) (A_SGE_DEBUG0_DBP_THREAD + (idx) * 4)
+#define NUM_SGE_DEBUG0_DBP_THREAD_INSTANCES 5
+
+#define SGE_WC_EGRS_BAR2_OFF_PF(idx) (A_SGE_WC_EGRS_BAR2_OFF_PF + (idx) * 4)
+#define NUM_SGE_WC_EGRS_BAR2_OFF_PF_INSTANCES 8
+
+#define SGE_WC_EGRS_BAR2_OFF_VF(idx) (A_SGE_WC_EGRS_BAR2_OFF_VF + (idx) * 4)
+#define NUM_SGE_WC_EGRS_BAR2_OFF_VF_INSTANCES 8
+
+#define PCIE_T6_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
+#define NUM_PCIE_T6_DMA_INSTANCES 2
+
+#define PCIE_T6_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
+#define NUM_PCIE_T6_CMD_INSTANCES 1
+
+#define PCIE_VF_256_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_PCIE_VF_256_INT_INSTANCES 128
+
+#define MPS_CLS_REQUEST_TRACE_MAC_DA_L(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_DA_L + (idx) * 32)
+#define NUM_MPS_CLS_REQUEST_TRACE_MAC_DA_L_INSTANCES 8
+
+#define MPS_CLS_REQUEST_TRACE_MAC_DA_H(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_DA_H + (idx) * 32)
+#define NUM_MPS_CLS_REQUEST_TRACE_MAC_DA_H_INSTANCES 8
+
+#define MPS_CLS_REQUEST_TRACE_MAC_SA_L(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_SA_L + (idx) * 32)
+#define NUM_MPS_CLS_REQUEST_TRACE_MAC_SA_L_INSTANCES 8
+
+#define MPS_CLS_REQUEST_TRACE_MAC_SA_H(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_SA_H + (idx) * 32)
+#define NUM_MPS_CLS_REQUEST_TRACE_MAC_SA_H_INSTANCES 8
+
+#define MPS_CLS_REQUEST_TRACE_PORT_VLAN(idx) (A_MPS_CLS_REQUEST_TRACE_PORT_VLAN + (idx) * 32)
+#define NUM_MPS_CLS_REQUEST_TRACE_PORT_VLAN_INSTANCES 8
+
+#define MPS_CLS_REQUEST_TRACE_ENCAP(idx) (A_MPS_CLS_REQUEST_TRACE_ENCAP + (idx) * 32)
+#define NUM_MPS_CLS_REQUEST_TRACE_ENCAP_INSTANCES 8
+
+#define MPS_CLS_RESULT_TRACE(idx) (A_MPS_CLS_RESULT_TRACE + (idx) * 4)
+#define NUM_MPS_CLS_RESULT_TRACE_INSTANCES 8
+
+#define MPS_CLS_DIPIPV4_ID_TABLE(idx) (A_MPS_CLS_DIPIPV4_ID_TABLE + (idx) * 8)
+#define NUM_MPS_CLS_DIPIPV4_ID_TABLE_INSTANCES 4
+
+#define MPS_CLS_DIPIPV4_MASK_TABLE(idx) (A_MPS_CLS_DIPIPV4_MASK_TABLE + (idx) * 8)
+#define NUM_MPS_CLS_DIPIPV4_MASK_TABLE_INSTANCES 4
+
+#define MPS_CLS_DIPIPV6ID_0_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_0_TABLE + (idx) * 32)
+#define NUM_MPS_CLS_DIPIPV6ID_0_TABLE_INSTANCES 2
+
+#define MPS_CLS_DIPIPV6ID_1_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_1_TABLE + (idx) * 32)
+#define NUM_MPS_CLS_DIPIPV6ID_1_TABLE_INSTANCES 2
+
+#define MPS_CLS_DIPIPV6ID_2_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_2_TABLE + (idx) * 32)
+#define NUM_MPS_CLS_DIPIPV6ID_2_TABLE_INSTANCES 2
+
+#define MPS_CLS_DIPIPV6ID_3_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_3_TABLE + (idx) * 32)
+#define NUM_MPS_CLS_DIPIPV6ID_3_TABLE_INSTANCES 2
+
+#define MPS_CLS_DIPIPV6MASK_0_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_0_TABLE + (idx) * 32)
+#define NUM_MPS_CLS_DIPIPV6MASK_0_TABLE_INSTANCES 2
+
+#define MPS_CLS_DIPIPV6MASK_1_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_1_TABLE + (idx) * 32)
+#define NUM_MPS_CLS_DIPIPV6MASK_1_TABLE_INSTANCES 2
+
+#define MPS_CLS_DIPIPV6MASK_2_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_2_TABLE + (idx) * 32)
+#define NUM_MPS_CLS_DIPIPV6MASK_2_TABLE_INSTANCES 2
+
+#define MPS_CLS_DIPIPV6MASK_3_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_3_TABLE + (idx) * 32)
+#define NUM_MPS_CLS_DIPIPV6MASK_3_TABLE_INSTANCES 2
+
+#define MPS_RX_HASH_LKP_TABLE(idx) (A_MPS_RX_HASH_LKP_TABLE + (idx) * 4)
+#define NUM_MPS_RX_HASH_LKP_TABLE_INSTANCES 4
+
+#define LE_DB_DBG_MATCH_DATA_MASK(idx) (A_LE_DB_DBG_MATCH_DATA_MASK + (idx) * 4)
+#define NUM_LE_DB_DBG_MATCH_DATA_MASK_INSTANCES 8
+
+#define LE_DB_DBG_MATCH_DATA(idx) (A_LE_DB_DBG_MATCH_DATA + (idx) * 4)
+#define NUM_LE_DB_DBG_MATCH_DATA_INSTANCES 8
+
+#define LE_DB_DBGI_REQ_DATA_T6(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4)
+#define NUM_LE_DB_DBGI_REQ_DATA_T6_INSTANCES 11
+
+#define LE_DB_DBGI_REQ_MASK_T6(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
+#define NUM_LE_DB_DBGI_REQ_MASK_T6_INSTANCES 11
+
+#define LE_DB_DBGI_RSP_DATA_T6(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4)
+#define NUM_LE_DB_DBGI_RSP_DATA_T6_INSTANCES 11
+
+#define LE_DB_ACTIVE_MASK_IPV6_T6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
+#define NUM_LE_DB_ACTIVE_MASK_IPV6_T6_INSTANCES 8
+
+#define LE_HASH_MASK_GEN_IPV4T6(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4)
+#define NUM_LE_HASH_MASK_GEN_IPV4T6_INSTANCES 8
+
+#define T6_LE_HASH_MASK_GEN_IPV6T5(idx) (A_T6_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4)
+#define NUM_T6_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 8
+
+#define LE_DB_PSV_FILTER_MASK_TUP_IPV4(idx) (A_LE_DB_PSV_FILTER_MASK_TUP_IPV4 + (idx) * 4)
+#define NUM_LE_DB_PSV_FILTER_MASK_TUP_IPV4_INSTANCES 3
+
+#define LE_DB_PSV_FILTER_MASK_FLT_IPV4(idx) (A_LE_DB_PSV_FILTER_MASK_FLT_IPV4 + (idx) * 4)
+#define NUM_LE_DB_PSV_FILTER_MASK_FLT_IPV4_INSTANCES 2
+
+#define LE_DB_PSV_FILTER_MASK_TUP_IPV6(idx) (A_LE_DB_PSV_FILTER_MASK_TUP_IPV6 + (idx) * 4)
+#define NUM_LE_DB_PSV_FILTER_MASK_TUP_IPV6_INSTANCES 9
+
+#define LE_DB_PSV_FILTER_MASK_FLT_IPV6(idx) (A_LE_DB_PSV_FILTER_MASK_FLT_IPV6 + (idx) * 4)
+#define NUM_LE_DB_PSV_FILTER_MASK_FLT_IPV6_INSTANCES 2
+
+#define LE_DB_SECOND_GEN_HASH_MASK_IPV4_T6(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4)
+#define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_T6_INSTANCES 8
+
+#define MC_DDRPHY_DP18_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
+#define NUM_MC_DDRPHY_DP18_T6_INSTANCES 9
+
+#define MC_CE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_MC_CE_ERR_DATA_T6_INSTANCES 16
+
+#define MC_UE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_MC_UE_ERR_DATA_T6_INSTANCES 16
+
+#define CIM_CTL_MAILBOX_VF_STATUS_T6(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4)
+#define NUM_CIM_CTL_MAILBOX_VF_STATUS_T6_INSTANCES 8
+
+#define CIM_CTL_MAILBOX_VFN_CTL_T6(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 4)
+#define NUM_CIM_CTL_MAILBOX_VFN_CTL_T6_INSTANCES 256
+
#define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
+#define EDC_T5_STRIDE (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
+#define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx)
+
/* registers for module SGE */
#define SGE_BASE_ADDR 0x1000
@@ -372,6 +508,10 @@
#define V_PIDX_T5(x) ((x) << S_PIDX_T5)
#define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)
+#define S_SYNC_T6 14
+#define V_SYNC_T6(x) ((x) << S_SYNC_T6)
+#define F_SYNC_T6 V_SYNC_T6(1U)
+
#define A_SGE_PF_GTS 0x4
#define S_INGRESSQID 16
@@ -764,6 +904,14 @@
#define V_PERR_PC_CHPI_RSP2(x) ((x) << S_PERR_PC_CHPI_RSP2)
#define F_PERR_PC_CHPI_RSP2 V_PERR_PC_CHPI_RSP2(1U)
+#define S_PERR_PC_RSP 23
+#define V_PERR_PC_RSP(x) ((x) << S_PERR_PC_RSP)
+#define F_PERR_PC_RSP V_PERR_PC_RSP(1U)
+
+#define S_PERR_PC_REQ 22
+#define V_PERR_PC_REQ(x) ((x) << S_PERR_PC_REQ)
+#define F_PERR_PC_REQ V_PERR_PC_REQ(1U)
+
#define A_SGE_INT_ENABLE1 0x1028
#define A_SGE_PERR_ENABLE1 0x102c
#define A_SGE_INT_CAUSE2 0x1030
@@ -908,6 +1056,26 @@
#define V_PERR_PC_DBP2(x) ((x) << S_PERR_PC_DBP2)
#define F_PERR_PC_DBP2 V_PERR_PC_DBP2(1U)
+#define S_DEQ_LL_PERR 21
+#define V_DEQ_LL_PERR(x) ((x) << S_DEQ_LL_PERR)
+#define F_DEQ_LL_PERR V_DEQ_LL_PERR(1U)
+
+#define S_ENQ_PERR 20
+#define V_ENQ_PERR(x) ((x) << S_ENQ_PERR)
+#define F_ENQ_PERR V_ENQ_PERR(1U)
+
+#define S_DEQ_OUT_PERR 19
+#define V_DEQ_OUT_PERR(x) ((x) << S_DEQ_OUT_PERR)
+#define F_DEQ_OUT_PERR V_DEQ_OUT_PERR(1U)
+
+#define S_BUF_PERR 18
+#define V_BUF_PERR(x) ((x) << S_BUF_PERR)
+#define F_BUF_PERR V_BUF_PERR(1U)
+
+#define S_PERR_DB_FIFO 3
+#define V_PERR_DB_FIFO(x) ((x) << S_PERR_DB_FIFO)
+#define F_PERR_DB_FIFO V_PERR_DB_FIFO(1U)
+
#define A_SGE_INT_ENABLE2 0x1034
#define A_SGE_PERR_ENABLE2 0x1038
#define A_SGE_INT_CAUSE3 0x103c
@@ -1040,6 +1208,14 @@
#define V_ERR_INV_CTXT0(x) ((x) << S_ERR_INV_CTXT0)
#define F_ERR_INV_CTXT0 V_ERR_INV_CTXT0(1U)
+#define S_DBP_TBUF_FULL 8
+#define V_DBP_TBUF_FULL(x) ((x) << S_DBP_TBUF_FULL)
+#define F_DBP_TBUF_FULL V_DBP_TBUF_FULL(1U)
+
+#define S_FATAL_WRE_LEN 7
+#define V_FATAL_WRE_LEN(x) ((x) << S_FATAL_WRE_LEN)
+#define F_FATAL_WRE_LEN V_FATAL_WRE_LEN(1U)
+
#define A_SGE_INT_ENABLE3 0x1040
#define A_SGE_FL_BUFFER_SIZE0 0x1044
@@ -1048,21 +1224,116 @@
#define V_SIZE(x) ((x) << S_SIZE)
#define G_SIZE(x) (((x) >> S_SIZE) & M_SIZE)
+#define S_T6_SIZE 4
+#define M_T6_SIZE 0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
#define A_SGE_FL_BUFFER_SIZE1 0x1048
+
+#define S_T6_SIZE 4
+#define M_T6_SIZE 0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
#define A_SGE_FL_BUFFER_SIZE2 0x104c
+
+#define S_T6_SIZE 4
+#define M_T6_SIZE 0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
#define A_SGE_FL_BUFFER_SIZE3 0x1050
+
+#define S_T6_SIZE 4
+#define M_T6_SIZE 0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
#define A_SGE_FL_BUFFER_SIZE4 0x1054
+
+#define S_T6_SIZE 4
+#define M_T6_SIZE 0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
#define A_SGE_FL_BUFFER_SIZE5 0x1058
+
+#define S_T6_SIZE 4
+#define M_T6_SIZE 0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
#define A_SGE_FL_BUFFER_SIZE6 0x105c
+
+#define S_T6_SIZE 4
+#define M_T6_SIZE 0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
#define A_SGE_FL_BUFFER_SIZE7 0x1060
+
+#define S_T6_SIZE 4
+#define M_T6_SIZE 0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
#define A_SGE_FL_BUFFER_SIZE8 0x1064
+
+#define S_T6_SIZE 4
+#define M_T6_SIZE 0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
#define A_SGE_FL_BUFFER_SIZE9 0x1068
+
+#define S_T6_SIZE 4
+#define M_T6_SIZE 0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
#define A_SGE_FL_BUFFER_SIZE10 0x106c
+
+#define S_T6_SIZE 4
+#define M_T6_SIZE 0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
#define A_SGE_FL_BUFFER_SIZE11 0x1070
+
+#define S_T6_SIZE 4
+#define M_T6_SIZE 0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
#define A_SGE_FL_BUFFER_SIZE12 0x1074
+
+#define S_T6_SIZE 4
+#define M_T6_SIZE 0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
#define A_SGE_FL_BUFFER_SIZE13 0x1078
+
+#define S_T6_SIZE 4
+#define M_T6_SIZE 0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
#define A_SGE_FL_BUFFER_SIZE14 0x107c
+
+#define S_T6_SIZE 4
+#define M_T6_SIZE 0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
#define A_SGE_FL_BUFFER_SIZE15 0x1080
+
+#define S_T6_SIZE 4
+#define M_T6_SIZE 0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
#define A_SGE_DBQ_CTXT_BADDR 0x1084
#define S_BASEADDR 3
@@ -1117,6 +1388,15 @@
#define V_CREDITCNTPACKING(x) ((x) << S_CREDITCNTPACKING)
#define G_CREDITCNTPACKING(x) (((x) >> S_CREDITCNTPACKING) & M_CREDITCNTPACKING)
+#define S_NULLPTR 20
+#define M_NULLPTR 0xfU
+#define V_NULLPTR(x) ((x) << S_NULLPTR)
+#define G_NULLPTR(x) (((x) >> S_NULLPTR) & M_NULLPTR)
+
+#define S_NULLPTREN 19
+#define V_NULLPTREN(x) ((x) << S_NULLPTREN)
+#define F_NULLPTREN V_NULLPTREN(1U)
+
#define A_SGE_CONM_CTRL 0x1094
#define S_EGRTHRESHOLD 8
@@ -1142,6 +1422,16 @@
#define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING)
#define G_EGRTHRESHOLDPACKING(x) (((x) >> S_EGRTHRESHOLDPACKING) & M_EGRTHRESHOLDPACKING)
+#define S_T6_EGRTHRESHOLDPACKING 16
+#define M_T6_EGRTHRESHOLDPACKING 0xffU
+#define V_T6_EGRTHRESHOLDPACKING(x) ((x) << S_T6_EGRTHRESHOLDPACKING)
+#define G_T6_EGRTHRESHOLDPACKING(x) (((x) >> S_T6_EGRTHRESHOLDPACKING) & M_T6_EGRTHRESHOLDPACKING)
+
+#define S_T6_EGRTHRESHOLD 8
+#define M_T6_EGRTHRESHOLD 0xffU
+#define V_T6_EGRTHRESHOLD(x) ((x) << S_T6_EGRTHRESHOLD)
+#define G_T6_EGRTHRESHOLD(x) (((x) >> S_T6_EGRTHRESHOLD) & M_T6_EGRTHRESHOLD)
+
#define A_SGE_TIMESTAMP_LO 0x1098
#define A_SGE_TIMESTAMP_HI 0x109c
@@ -1217,6 +1507,21 @@
#define V_LP_COUNT_T5(x) ((x) << S_LP_COUNT_T5)
#define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT_T5) & M_LP_COUNT_T5)
+#define S_VFIFO_CNT 15
+#define M_VFIFO_CNT 0x1ffffU
+#define V_VFIFO_CNT(x) ((x) << S_VFIFO_CNT)
+#define G_VFIFO_CNT(x) (((x) >> S_VFIFO_CNT) & M_VFIFO_CNT)
+
+#define S_COAL_CTL_FIFO_CNT 8
+#define M_COAL_CTL_FIFO_CNT 0x3fU
+#define V_COAL_CTL_FIFO_CNT(x) ((x) << S_COAL_CTL_FIFO_CNT)
+#define G_COAL_CTL_FIFO_CNT(x) (((x) >> S_COAL_CTL_FIFO_CNT) & M_COAL_CTL_FIFO_CNT)
+
+#define S_MERGE_FIFO_CNT 0
+#define M_MERGE_FIFO_CNT 0x3fU
+#define V_MERGE_FIFO_CNT(x) ((x) << S_MERGE_FIFO_CNT)
+#define G_MERGE_FIFO_CNT(x) (((x) >> S_MERGE_FIFO_CNT) & M_MERGE_FIFO_CNT)
+
#define A_SGE_DOORBELL_CONTROL 0x10a8
#define S_HINTDEPTHCTL 27
@@ -1286,6 +1591,32 @@
#define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
#define F_DROPPED_DB V_DROPPED_DB(1U)
+#define S_T6_DROP_TIMEOUT 7
+#define M_T6_DROP_TIMEOUT 0x3fU
+#define V_T6_DROP_TIMEOUT(x) ((x) << S_T6_DROP_TIMEOUT)
+#define G_T6_DROP_TIMEOUT(x) (((x) >> S_T6_DROP_TIMEOUT) & M_T6_DROP_TIMEOUT)
+
+#define S_INVONDBSYNC 6
+#define V_INVONDBSYNC(x) ((x) << S_INVONDBSYNC)
+#define F_INVONDBSYNC V_INVONDBSYNC(1U)
+
+#define S_INVONGTSSYNC 5
+#define V_INVONGTSSYNC(x) ((x) << S_INVONGTSSYNC)
+#define F_INVONGTSSYNC V_INVONGTSSYNC(1U)
+
+#define S_DB_DBG_EN 4
+#define V_DB_DBG_EN(x) ((x) << S_DB_DBG_EN)
+#define F_DB_DBG_EN V_DB_DBG_EN(1U)
+
+#define S_GTS_DBG_TIMER_REG 1
+#define M_GTS_DBG_TIMER_REG 0x7U
+#define V_GTS_DBG_TIMER_REG(x) ((x) << S_GTS_DBG_TIMER_REG)
+#define G_GTS_DBG_TIMER_REG(x) (((x) >> S_GTS_DBG_TIMER_REG) & M_GTS_DBG_TIMER_REG)
+
+#define S_GTS_DBG_EN 0
+#define V_GTS_DBG_EN(x) ((x) << S_GTS_DBG_EN)
+#define F_GTS_DBG_EN V_GTS_DBG_EN(1U)
+
#define A_SGE_DROPPED_DOORBELL 0x10ac
#define A_SGE_DOORBELL_THROTTLE_CONTROL 0x10b0
@@ -1331,6 +1662,11 @@
#define V_LL_READ_WAIT_DISABLE(x) ((x) << S_LL_READ_WAIT_DISABLE)
#define F_LL_READ_WAIT_DISABLE V_LL_READ_WAIT_DISABLE(1U)
+#define S_TSCALE 28
+#define M_TSCALE 0xfU
+#define V_TSCALE(x) ((x) << S_TSCALE)
+#define G_TSCALE(x) (((x) >> S_TSCALE) & M_TSCALE)
+
#define A_SGE_TIMER_VALUE_0_AND_1 0x10b8
#define S_TIMERVALUE0 16
@@ -1397,6 +1733,39 @@
#define V_MAXRSPCNT1(x) ((x) << S_MAXRSPCNT1)
#define G_MAXRSPCNT1(x) (((x) >> S_MAXRSPCNT1) & M_MAXRSPCNT1)
+#define A_SGE_GK_CONTROL 0x10c4
+
+#define S_EN_FLM_FIFTH 29
+#define V_EN_FLM_FIFTH(x) ((x) << S_EN_FLM_FIFTH)
+#define F_EN_FLM_FIFTH V_EN_FLM_FIFTH(1U)
+
+#define S_FL_PROG_THRESH 20
+#define M_FL_PROG_THRESH 0x1ffU
+#define V_FL_PROG_THRESH(x) ((x) << S_FL_PROG_THRESH)
+#define G_FL_PROG_THRESH(x) (((x) >> S_FL_PROG_THRESH) & M_FL_PROG_THRESH)
+
+#define S_COAL_ALL_THREAD 19
+#define V_COAL_ALL_THREAD(x) ((x) << S_COAL_ALL_THREAD)
+#define F_COAL_ALL_THREAD V_COAL_ALL_THREAD(1U)
+
+#define S_EN_PSHB 18
+#define V_EN_PSHB(x) ((x) << S_EN_PSHB)
+#define F_EN_PSHB V_EN_PSHB(1U)
+
+#define S_EN_DB_FIFTH 17
+#define V_EN_DB_FIFTH(x) ((x) << S_EN_DB_FIFTH)
+#define F_EN_DB_FIFTH V_EN_DB_FIFTH(1U)
+
+#define S_DB_PROG_THRESH 8
+#define M_DB_PROG_THRESH 0x1ffU
+#define V_DB_PROG_THRESH(x) ((x) << S_DB_PROG_THRESH)
+#define G_DB_PROG_THRESH(x) (((x) >> S_DB_PROG_THRESH) & M_DB_PROG_THRESH)
+
+#define S_100NS_TIMER 0
+#define M_100NS_TIMER 0xffU
+#define V_100NS_TIMER(x) ((x) << S_100NS_TIMER)
+#define G_100NS_TIMER(x) (((x) >> S_100NS_TIMER) & M_100NS_TIMER)
+
#define A_SGE_PD_RSP_CREDIT23 0x10c8
#define S_RSPCREDITEN2 31
@@ -1427,6 +1796,23 @@
#define V_MAXRSPCNT3(x) ((x) << S_MAXRSPCNT3)
#define G_MAXRSPCNT3(x) (((x) >> S_MAXRSPCNT3) & M_MAXRSPCNT3)
+#define A_SGE_GK_CONTROL2 0x10c8
+
+#define S_DBQ_TIMER_TICK 16
+#define M_DBQ_TIMER_TICK 0xffffU
+#define V_DBQ_TIMER_TICK(x) ((x) << S_DBQ_TIMER_TICK)
+#define G_DBQ_TIMER_TICK(x) (((x) >> S_DBQ_TIMER_TICK) & M_DBQ_TIMER_TICK)
+
+#define S_FL_MERGE_CNT_THRESH 8
+#define M_FL_MERGE_CNT_THRESH 0xfU
+#define V_FL_MERGE_CNT_THRESH(x) ((x) << S_FL_MERGE_CNT_THRESH)
+#define G_FL_MERGE_CNT_THRESH(x) (((x) >> S_FL_MERGE_CNT_THRESH) & M_FL_MERGE_CNT_THRESH)
+
+#define S_MERGE_CNT_THRESH 0
+#define M_MERGE_CNT_THRESH 0x3fU
+#define V_MERGE_CNT_THRESH(x) ((x) << S_MERGE_CNT_THRESH)
+#define G_MERGE_CNT_THRESH(x) (((x) >> S_MERGE_CNT_THRESH) & M_MERGE_CNT_THRESH)
+
#define A_SGE_DEBUG_INDEX 0x10cc
#define A_SGE_DEBUG_DATA_HIGH 0x10d0
#define A_SGE_DEBUG_DATA_LOW 0x10d4
@@ -1553,6 +1939,30 @@
#define V_ERR_RX_CPL_PACKET_SIZE0(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE0)
#define F_ERR_RX_CPL_PACKET_SIZE0 V_ERR_RX_CPL_PACKET_SIZE0(1U)
+#define S_ERR_ISHIFT_UR1 31
+#define V_ERR_ISHIFT_UR1(x) ((x) << S_ERR_ISHIFT_UR1)
+#define F_ERR_ISHIFT_UR1 V_ERR_ISHIFT_UR1(1U)
+
+#define S_ERR_ISHIFT_UR0 30
+#define V_ERR_ISHIFT_UR0(x) ((x) << S_ERR_ISHIFT_UR0)
+#define F_ERR_ISHIFT_UR0 V_ERR_ISHIFT_UR0(1U)
+
+#define S_ERR_TH3_MAX_FETCH 14
+#define V_ERR_TH3_MAX_FETCH(x) ((x) << S_ERR_TH3_MAX_FETCH)
+#define F_ERR_TH3_MAX_FETCH V_ERR_TH3_MAX_FETCH(1U)
+
+#define S_ERR_TH2_MAX_FETCH 13
+#define V_ERR_TH2_MAX_FETCH(x) ((x) << S_ERR_TH2_MAX_FETCH)
+#define F_ERR_TH2_MAX_FETCH V_ERR_TH2_MAX_FETCH(1U)
+
+#define S_ERR_TH1_MAX_FETCH 12
+#define V_ERR_TH1_MAX_FETCH(x) ((x) << S_ERR_TH1_MAX_FETCH)
+#define F_ERR_TH1_MAX_FETCH V_ERR_TH1_MAX_FETCH(1U)
+
+#define S_ERR_TH0_MAX_FETCH 11
+#define V_ERR_TH0_MAX_FETCH(x) ((x) << S_ERR_TH0_MAX_FETCH)
+#define F_ERR_TH0_MAX_FETCH V_ERR_TH0_MAX_FETCH(1U)
+
#define A_SGE_INT_ENABLE4 0x10e0
#define A_SGE_STAT_TOTAL 0x10e4
#define A_SGE_STAT_MATCH 0x10e8
@@ -1587,6 +1997,11 @@
#define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
#define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5)
+#define S_T6_STATMODE 0
+#define M_T6_STATMODE 0xfU
+#define V_T6_STATMODE(x) ((x) << S_T6_STATMODE)
+#define G_T6_STATMODE(x) (((x) >> S_T6_STATMODE) & M_T6_STATMODE)
+
#define A_SGE_HINT_CFG 0x10f0
#define S_HINTSALLOWEDNOHDR 6
@@ -1660,6 +2075,7 @@
#define V_MINTAG0(x) ((x) << S_MINTAG0)
#define G_MINTAG0(x) (((x) >> S_MINTAG0) & M_MINTAG0)
+#define A_SGE_IDMA0_DROP_CNT 0x1104
#define A_SGE_SHARED_TAG_POOL_CFG 0x1108
#define S_TAGPOOLTOTAL 0
@@ -1667,6 +2083,7 @@
#define V_TAGPOOLTOTAL(x) ((x) << S_TAGPOOLTOTAL)
#define G_TAGPOOLTOTAL(x) (((x) >> S_TAGPOOLTOTAL) & M_TAGPOOLTOTAL)
+#define A_SGE_IDMA1_DROP_CNT 0x1108
#define A_SGE_INT_CAUSE5 0x110c
#define S_ERR_T_RXCRC 31
@@ -1963,6 +2380,90 @@
#define V_EDMA0_SLEEP_REQ(x) ((x) << S_EDMA0_SLEEP_REQ)
#define F_EDMA0_SLEEP_REQ V_EDMA0_SLEEP_REQ(1U)
+#define A_SGE_INT_CAUSE6 0x1128
+
+#define S_ERR_DB_SYNC 21
+#define V_ERR_DB_SYNC(x) ((x) << S_ERR_DB_SYNC)
+#define F_ERR_DB_SYNC V_ERR_DB_SYNC(1U)
+
+#define S_ERR_GTS_SYNC 20
+#define V_ERR_GTS_SYNC(x) ((x) << S_ERR_GTS_SYNC)
+#define F_ERR_GTS_SYNC V_ERR_GTS_SYNC(1U)
+
+#define S_FATAL_LARGE_COAL 19
+#define V_FATAL_LARGE_COAL(x) ((x) << S_FATAL_LARGE_COAL)
+#define F_FATAL_LARGE_COAL V_FATAL_LARGE_COAL(1U)
+
+#define S_PL_BAR2_FRM_ERR 18
+#define V_PL_BAR2_FRM_ERR(x) ((x) << S_PL_BAR2_FRM_ERR)
+#define F_PL_BAR2_FRM_ERR V_PL_BAR2_FRM_ERR(1U)
+
+#define S_SILENT_DROP_TX_COAL 17
+#define V_SILENT_DROP_TX_COAL(x) ((x) << S_SILENT_DROP_TX_COAL)
+#define F_SILENT_DROP_TX_COAL V_SILENT_DROP_TX_COAL(1U)
+
+#define S_ERR_INV_CTXT4 16
+#define V_ERR_INV_CTXT4(x) ((x) << S_ERR_INV_CTXT4)
+#define F_ERR_INV_CTXT4 V_ERR_INV_CTXT4(1U)
+
+#define S_ERR_BAD_DB_PIDX4 15
+#define V_ERR_BAD_DB_PIDX4(x) ((x) << S_ERR_BAD_DB_PIDX4)
+#define F_ERR_BAD_DB_PIDX4 V_ERR_BAD_DB_PIDX4(1U)
+
+#define S_ERR_BAD_UPFL_INC_CREDIT4 14
+#define V_ERR_BAD_UPFL_INC_CREDIT4(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT4)
+#define F_ERR_BAD_UPFL_INC_CREDIT4 V_ERR_BAD_UPFL_INC_CREDIT4(1U)
+
+#define S_FATAL_TAG_MISMATCH 13
+#define V_FATAL_TAG_MISMATCH(x) ((x) << S_FATAL_TAG_MISMATCH)
+#define F_FATAL_TAG_MISMATCH V_FATAL_TAG_MISMATCH(1U)
+
+#define S_FATAL_ENQ_CTL_RDY 12
+#define V_FATAL_ENQ_CTL_RDY(x) ((x) << S_FATAL_ENQ_CTL_RDY)
+#define F_FATAL_ENQ_CTL_RDY V_FATAL_ENQ_CTL_RDY(1U)
+
+#define S_ERR_PC_RSP_LEN3 11
+#define V_ERR_PC_RSP_LEN3(x) ((x) << S_ERR_PC_RSP_LEN3)
+#define F_ERR_PC_RSP_LEN3 V_ERR_PC_RSP_LEN3(1U)
+
+#define S_ERR_PC_RSP_LEN2 10
+#define V_ERR_PC_RSP_LEN2(x) ((x) << S_ERR_PC_RSP_LEN2)
+#define F_ERR_PC_RSP_LEN2 V_ERR_PC_RSP_LEN2(1U)
+
+#define S_ERR_PC_RSP_LEN1 9
+#define V_ERR_PC_RSP_LEN1(x) ((x) << S_ERR_PC_RSP_LEN1)
+#define F_ERR_PC_RSP_LEN1 V_ERR_PC_RSP_LEN1(1U)
+
+#define S_ERR_PC_RSP_LEN0 8
+#define V_ERR_PC_RSP_LEN0(x) ((x) << S_ERR_PC_RSP_LEN0)
+#define F_ERR_PC_RSP_LEN0 V_ERR_PC_RSP_LEN0(1U)
+
+#define S_FATAL_ENQ2LL_VLD 7
+#define V_FATAL_ENQ2LL_VLD(x) ((x) << S_FATAL_ENQ2LL_VLD)
+#define F_FATAL_ENQ2LL_VLD V_FATAL_ENQ2LL_VLD(1U)
+
+#define S_FATAL_LL_EMPTY 6
+#define V_FATAL_LL_EMPTY(x) ((x) << S_FATAL_LL_EMPTY)
+#define F_FATAL_LL_EMPTY V_FATAL_LL_EMPTY(1U)
+
+#define S_FATAL_OFF_WDENQ 5
+#define V_FATAL_OFF_WDENQ(x) ((x) << S_FATAL_OFF_WDENQ)
+#define F_FATAL_OFF_WDENQ V_FATAL_OFF_WDENQ(1U)
+
+#define S_FATAL_DEQ_DRDY 3
+#define M_FATAL_DEQ_DRDY 0x3U
+#define V_FATAL_DEQ_DRDY(x) ((x) << S_FATAL_DEQ_DRDY)
+#define G_FATAL_DEQ_DRDY(x) (((x) >> S_FATAL_DEQ_DRDY) & M_FATAL_DEQ_DRDY)
+
+#define S_FATAL_OUTP_DRDY 1
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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