svn commit: r318002 - head/sys/dev/iwm

Adrian Chadd adrian at FreeBSD.org
Tue May 9 02:41:35 UTC 2017


Author: adrian
Date: Tue May  9 02:41:33 2017
New Revision: 318002
URL: https://svnweb.freebsd.org/changeset/base/318002

Log:
  [iwm] iwm_{read,write}_prph() don't grab the nic lock in iwm themselves.
  
  * Fix a couple of cases where the nic lock ended up not being grabbed
    during an iwm_read_prph() or iwm_write_prph().
  
  Obtained from:	dragonflybsd.git 6c5470f2db219c61e362c981fea969d97e1b8293

Modified:
  head/sys/dev/iwm/if_iwm.c
  head/sys/dev/iwm/if_iwm_pcie_trans.c

Modified: head/sys/dev/iwm/if_iwm.c
==============================================================================
--- head/sys/dev/iwm/if_iwm.c	Tue May  9 02:38:23 2017	(r318001)
+++ head/sys/dev/iwm/if_iwm.c	Tue May  9 02:41:33 2017	(r318002)
@@ -1294,9 +1294,9 @@ iwm_stop_device(struct iwm_softc *sc)
 
 	/* stop tx and rx.  tx and rx bits, as usual, are from if_iwn */
 
-	iwm_write_prph(sc, IWM_SCD_TXFACT, 0);
-
 	if (iwm_nic_lock(sc)) {
+		iwm_write_prph(sc, IWM_SCD_TXFACT, 0);
+
 		/* Stop each Tx DMA channel */
 		for (chnl = 0; chnl < IWM_FH_TCSR_CHNL_NUM; chnl++) {
 			IWM_WRITE(sc,
@@ -1324,8 +1324,10 @@ iwm_stop_device(struct iwm_softc *sc)
 
 	if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) {
 		/* Power-down device's busmaster DMA clocks */
-		iwm_write_prph(sc, IWM_APMG_CLK_DIS_REG,
-		    IWM_APMG_CLK_VAL_DMA_CLK_RQT);
+		if (iwm_nic_lock(sc)) {
+			iwm_write_prph(sc, IWM_APMG_CLK_DIS_REG,
+			    IWM_APMG_CLK_VAL_DMA_CLK_RQT);
+		}
 		DELAY(5);
 	}
 
@@ -1622,8 +1624,6 @@ iwm_trans_pcie_fw_alive(struct iwm_softc
 
 	iwm_ict_reset(sc);
 
-	iwm_nic_unlock(sc);
-
 	sc->scd_base_addr = iwm_read_prph(sc, IWM_SCD_SRAM_BASE_ADDR);
 	if (scd_base_addr != 0 &&
 	    scd_base_addr != sc->scd_base_addr) {
@@ -1632,6 +1632,8 @@ iwm_trans_pcie_fw_alive(struct iwm_softc
 		    __func__, sc->scd_base_addr, scd_base_addr);
 	}
 
+	iwm_nic_unlock(sc);
+
 	/* reset context data, TX status and translation data */
 	error = iwm_write_mem(sc,
 	    sc->scd_base_addr + IWM_SCD_CONTEXT_MEM_LOWER_BOUND,
@@ -2591,9 +2593,11 @@ iwm_pcie_load_given_ucode(struct iwm_sof
 
 	if (image->is_dual_cpus) {
 		/* set CPU2 header address */
-                iwm_write_prph(sc,
-			       IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
-			       IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE);
+		if (iwm_nic_lock(sc)) {
+			iwm_write_prph(sc,
+				       IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
+				       IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE);
+		}
 
 		/* load to FW the binary sections of CPU2 */
 		ret = iwm_pcie_load_cpu_sections(sc, image, 2,
@@ -2622,7 +2626,10 @@ iwm_pcie_load_given_ucode_8000(struct iw
 
 	/* configure the ucode to be ready to get the secured image */
 	/* release CPU reset */
-	iwm_write_prph(sc, IWM_RELEASE_CPU_RESET, IWM_RELEASE_CPU_RESET_BIT);
+	if (iwm_nic_lock(sc)) {
+		iwm_write_prph(sc, IWM_RELEASE_CPU_RESET,
+		    IWM_RELEASE_CPU_RESET_BIT);
+	}
 
 	/* load to FW the binary Secured sections of CPU1 */
 	ret = iwm_pcie_load_cpu_sections_8000(sc, image, 1,
@@ -2876,10 +2883,14 @@ iwm_mvm_load_ucode_wait_alive(struct iwm
 	IWM_LOCK(sc);
 	if (error) {
 		if (sc->cfg->device_family == IWM_DEVICE_FAMILY_8000) {
+			uint32_t a = 0x5a5a5a5a, b = 0x5a5a5a5a;
+			if (iwm_nic_lock(sc)) {
+				a = iwm_read_prph(sc, IWM_SB_CPU_1_STATUS);
+				b = iwm_read_prph(sc, IWM_SB_CPU_2_STATUS);
+			}
 			device_printf(sc->sc_dev,
 			    "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
-			    iwm_read_prph(sc, IWM_SB_CPU_1_STATUS),
-			    iwm_read_prph(sc, IWM_SB_CPU_2_STATUS));
+			    a, b);
 		}
 		sc->cur_ucode = old_type;
 		return error;

Modified: head/sys/dev/iwm/if_iwm_pcie_trans.c
==============================================================================
--- head/sys/dev/iwm/if_iwm_pcie_trans.c	Tue May  9 02:38:23 2017	(r318001)
+++ head/sys/dev/iwm/if_iwm_pcie_trans.c	Tue May  9 02:41:33 2017	(r318002)
@@ -499,11 +499,15 @@ iwm_apm_init(struct iwm_softc *sc)
 		 * just to discard the value. But that's the way the hardware
 		 * seems to like it.
 		 */
-		iwm_read_prph(sc, IWM_OSC_CLK);
-		iwm_read_prph(sc, IWM_OSC_CLK);
+		if (iwm_nic_lock(sc)) {
+			iwm_read_prph(sc, IWM_OSC_CLK);
+			iwm_read_prph(sc, IWM_OSC_CLK);
+		}
 		iwm_set_bits_prph(sc, IWM_OSC_CLK, IWM_OSC_CLK_FORCE_CONTROL);
-		iwm_read_prph(sc, IWM_OSC_CLK);
-		iwm_read_prph(sc, IWM_OSC_CLK);
+		if (iwm_nic_lock(sc)) {
+			iwm_read_prph(sc, IWM_OSC_CLK);
+			iwm_read_prph(sc, IWM_OSC_CLK);
+		}
 	}
 
 	/*
@@ -514,8 +518,10 @@ iwm_apm_init(struct iwm_softc *sc)
 	 * set by default in "CLK_CTRL_REG" after reset.
 	 */
 	if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) {
-		iwm_write_prph(sc, IWM_APMG_CLK_EN_REG,
-		    IWM_APMG_CLK_VAL_DMA_CLK_RQT);
+		if (iwm_nic_lock(sc)) {
+			iwm_write_prph(sc, IWM_APMG_CLK_EN_REG,
+			    IWM_APMG_CLK_VAL_DMA_CLK_RQT);
+		}
 		DELAY(20);
 
 		/* Disable L1-Active */
@@ -523,8 +529,10 @@ iwm_apm_init(struct iwm_softc *sc)
 		    IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 
 		/* Clear the interrupt in APMG if the NIC is in RFKILL */
-		iwm_write_prph(sc, IWM_APMG_RTC_INT_STT_REG,
-		    IWM_APMG_RTC_INT_STT_RFKILL);
+		if (iwm_nic_lock(sc)) {
+			iwm_write_prph(sc, IWM_APMG_RTC_INT_STT_REG,
+			    IWM_APMG_RTC_INT_STT_RFKILL);
+		}
 	}
  out:
 	if (error)
@@ -626,12 +634,12 @@ iwm_pcie_set_cmd_in_flight(struct iwm_so
 		IWM_SETBITS(sc, IWM_CSR_GP_CNTRL,
 		    IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 
-                ret = iwm_poll_bit(sc, IWM_CSR_GP_CNTRL,
+		ret = iwm_poll_bit(sc, IWM_CSR_GP_CNTRL,
 		    IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
 		    (IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
 		     IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
 		    15000);
-                if (ret == 0) {
+		if (ret == 0) {
 			IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL,
 			    IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 			device_printf(sc->sc_dev,


More information about the svn-src-all mailing list