svn commit: r315451 - in head/sys: arm/mv conf

Andrew Turner andrew at FreeBSD.org
Fri Mar 17 12:59:18 UTC 2017 

Author: andrew
Date: Fri Mar 17 12:59:16 2017
New Revision: 315451
URL: https://svnweb.freebsd.org/changeset/base/315451

Log:
  Remove code for Marvell SoCs that lack a kernel config.
  
  It seems to be old code from the armv6 project branch that never had a
  kernel config.
  
  Reviewed by:	mmel
  Sponsored by:	ABT Systems Lrd
  Differential Revision:	https://reviews.freebsd.org/D7166

Modified:
  head/sys/arm/mv/mv_common.c
  head/sys/arm/mv/mv_machdep.c
  head/sys/arm/mv/mvreg.h
  head/sys/arm/mv/mvwin.h
  head/sys/conf/options.arm

Modified: head/sys/arm/mv/mv_common.c
==============================================================================
--- head/sys/arm/mv/mv_common.c	Fri Mar 17 12:45:53 2017	(r315450)
+++ head/sys/arm/mv/mv_common.c	Fri Mar 17 12:59:16 2017	(r315451)
@@ -76,9 +76,7 @@ MALLOC_DEFINE(M_IDMA, "idma", "idma dma 
 
 static int win_eth_can_remap(int i);
 
-#ifndef SOC_MV_FREY
 static int decode_win_cpu_valid(void);
-#endif
 static int decode_win_usb_valid(void);
 static int decode_win_usb3_valid(void);
 static int decode_win_eth_valid(void);
@@ -88,9 +86,7 @@ static int decode_win_sata_valid(void);
 static int decode_win_idma_valid(void);
 static int decode_win_xor_valid(void);
 
-#ifndef SOC_MV_FREY
 static void decode_win_cpu_setup(void);
-#endif
 #ifdef SOC_MV_ARMADAXP
 static int decode_win_sdram_fixup(void);
 #endif
@@ -359,7 +355,7 @@ uint32_t
 soc_power_ctrl_get(uint32_t mask)
 {
 
-#if !defined(SOC_MV_ORION) && !defined(SOC_MV_LOKIPLUS) && !defined(SOC_MV_FREY)
+#if !defined(SOC_MV_ORION)
 	if (mask != CPU_PM_CTRL_NONE)
 		mask &= read_cpu_ctrl(CPU_PM_CTRL);
 
@@ -377,7 +373,7 @@ void
 soc_power_ctrl_set(uint32_t mask)
 {
 
-#if !defined(SOC_MV_ORION) && !defined(SOC_MV_LOKIPLUS)
+#if !defined(SOC_MV_ORION)
 	if (mask != CPU_PM_CTRL_NONE)
 		write_cpu_ctrl(CPU_PM_CTRL, mask);
 #endif
@@ -569,7 +565,6 @@ soc_decode_win(void)
 		return(err);
 #endif
 
-#ifndef SOC_MV_FREY
 	if (!decode_win_cpu_valid() || !decode_win_usb_valid() ||
 	    !decode_win_eth_valid() || !decode_win_idma_valid() ||
 	    !decode_win_pcie_valid() || !decode_win_sata_valid() ||
@@ -577,13 +572,6 @@ soc_decode_win(void)
 		return (EINVAL);
 
 	decode_win_cpu_setup();
-#else
-	if (!decode_win_usb_valid() ||
-	    !decode_win_eth_valid() || !decode_win_idma_valid() ||
-	    !decode_win_pcie_valid() || !decode_win_sata_valid() ||
-	    !decode_win_xor_valid() || !decode_win_usb3_valid())
-		return (EINVAL);
-#endif
 	if (MV_DUMP_WIN)
 		soc_dump_decode_win();
 
@@ -598,7 +586,6 @@ soc_decode_win(void)
 /**************************************************************************
  * Decode windows registers accessors
  **************************************************************************/
-#if !defined(SOC_MV_FREY)
 WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
 WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
 WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
@@ -607,7 +594,6 @@ WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_C
 WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
 WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
 WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
-#endif
 
 WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL)
 WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE)
@@ -712,7 +698,6 @@ static inline uint32_t ddr_sz_read(int i
 }
 #endif
 
-#if !defined(SOC_MV_FREY)
 /**************************************************************************
  * Decode windows helper routines
  **************************************************************************/
@@ -935,7 +920,6 @@ decode_win_cpu_setup(void)
 			    cpu_wins[i].size, cpu_wins[i].remap);
 
 }
-#endif
 
 #ifdef SOC_MV_ARMADAXP
 static int
@@ -1294,11 +1278,7 @@ decode_win_eth_dump(u_long base)
 	    win_eth_epap_read(base));
 }
 
-#if defined(SOC_MV_LOKIPLUS)
-#define MV_WIN_ETH_DDR_TRGT(n)	0
-#else
 #define MV_WIN_ETH_DDR_TRGT(n)	ddr_target(n)
-#endif
 
 static void
 decode_win_eth_setup(u_long base)

Modified: head/sys/arm/mv/mv_machdep.c
==============================================================================
--- head/sys/arm/mv/mv_machdep.c	Fri Mar 17 12:45:53 2017	(r315450)
+++ head/sys/arm/mv/mv_machdep.c	Fri Mar 17 12:59:16 2017	(r315451)
@@ -244,14 +244,9 @@ platform_late_init(void)
 	/*
 	 * Re-initialise decode windows
 	 */
-#if !defined(SOC_MV_FREY)
 	if (soc_decode_win() != 0)
 		printf("WARNING: could not re-initialise decode windows! "
 		    "Running with existing settings...\n");
-#else
-	/* Disable watchdog and timers */
-	write_cpu_ctrl(CPU_TIMERS_BASE + CPU_TIMER_CONTROL, 0);
-#endif
 #if defined(SOC_MV_ARMADAXP)
 #if !defined(SMP)
 	/* For SMP case it should be initialized after APs are booted */

Modified: head/sys/arm/mv/mvreg.h
==============================================================================
--- head/sys/arm/mv/mvreg.h	Fri Mar 17 12:45:53 2017	(r315450)
+++ head/sys/arm/mv/mvreg.h	Fri Mar 17 12:59:16 2017	(r315451)
@@ -52,18 +52,6 @@
 #define ENDPOINT_IRQ_MASK(n)	0x30
 #define ENDPOINT_IRQ_MASK_HI(n)	0x34
 #define ENDPOINT_IRQ_CAUSE_SELECT 0x38
-#elif defined (SOC_MV_LOKIPLUS) || defined (SOC_MV_FREY)
-#define IRQ_CAUSE		0x0
-#define IRQ_MASK		0x4
-#define FIQ_MASK		0x8
-#define ENDPOINT_IRQ_MASK(n)	(0xC + (n) * 4)
-#define IRQ_CAUSE_HI		(-1)		/* Fake defines for unified */
-#define IRQ_MASK_HI		(-1)		/* interrupt controller code */
-#define FIQ_MASK_HI		(-1)
-#define ENDPOINT_IRQ_MASK_HI(n)	(-1)
-#define ENDPOINT_IRQ_MASK_ERROR(n) (-1)
-#define IRQ_CAUSE_ERROR		(-1)
-#define IRQ_MASK_ERROR		(-1)
 #elif defined (SOC_MV_ARMADAXP)
 #define IRQ_CAUSE		0x18
 #define IRQ_MASK		0x30
@@ -84,17 +72,7 @@
 #define IRQ_MASK_ERROR		(-1)		/* interrupt controller code */
 #endif
 
-#if defined(SOC_MV_FREY)
-#define BRIDGE_IRQ_CAUSE	0x118
-#define IRQ_TIMER0		0x00000002
-#define IRQ_TIMER1		0x00000004
-#define IRQ_TIMER_WD		0x00000008
-
-#define BRIDGE_IRQ_MASK		0x11c
-#define IRQ_TIMER0_MASK		0x00000002
-#define IRQ_TIMER1_MASK		0x00000004
-#define IRQ_TIMER_WD_MASK	0x00000008
-#elif defined(SOC_MV_ARMADAXP)
+#if defined(SOC_MV_ARMADAXP)
 #define BRIDGE_IRQ_CAUSE	0x68
 #define IRQ_TIMER0		0x00000001
 #define IRQ_TIMER1		0x00000002
@@ -113,17 +91,10 @@
 #define IRQ_TIMER_WD_MASK	0x00000008
 #endif
 
-#if defined(SOC_MV_LOKIPLUS) || defined(SOC_MV_FREY)
-#define IRQ_CPU_SELF_CLR	IRQ_CPU_SELF
-#define IRQ_TIMER0_CLR		IRQ_TIMER0
-#define IRQ_TIMER1_CLR		IRQ_TIMER1
-#define IRQ_TIMER_WD_CLR	IRQ_TIMER_WD
-#else
 #define IRQ_CPU_SELF_CLR	(~IRQ_CPU_SELF)
 #define IRQ_TIMER0_CLR		(~IRQ_TIMER0)
 #define IRQ_TIMER1_CLR		(~IRQ_TIMER1)
 #define IRQ_TIMER_WD_CLR	(~IRQ_TIMER_WD)
-#endif
 
 /*
  * System reset
@@ -348,22 +319,14 @@
 #define GPIO2IRQ(gpio)		((gpio) + NIRQ)
 #define IRQ2GPIO(irq)		((irq) - NIRQ)
 
-#if defined(SOC_MV_ORION) || defined(SOC_MV_LOKIPLUS)
+#if defined(SOC_MV_ORION)
 #define SAMPLE_AT_RESET		0x10
 #elif defined(SOC_MV_KIRKWOOD)
 #define SAMPLE_AT_RESET		0x30
-#elif defined(SOC_MV_FREY)
-#define SAMPLE_AT_RESET		0x100
 #elif defined(SOC_MV_ARMADA38X)
 #define SAMPLE_AT_RESET		0x400
 #endif
-#if defined(SOC_MV_DISCOVERY)
-#define SAMPLE_AT_RESET_LO	0x30
-#define SAMPLE_AT_RESET_HI	0x34
-#elif defined(SOC_MV_DOVE)
-#define SAMPLE_AT_RESET_LO	0x14
-#define SAMPLE_AT_RESET_HI	0x18
-#elif defined(SOC_MV_ARMADAXP)
+#if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_ARMADAXP)
 #define SAMPLE_AT_RESET_LO	0x30
 #define SAMPLE_AT_RESET_HI	0x34
 #endif
@@ -377,9 +340,6 @@
 #elif defined(SOC_MV_DISCOVERY)
 #define TCLK_MASK		0x00000180
 #define TCLK_SHIFT		0x07
-#elif defined(SOC_MV_LOKIPLUS)
-#define TCLK_MASK		0x0000F000
-#define TCLK_SHIFT		0x0C
 #elif defined(SOC_MV_ARMADA38X)
 #define TCLK_MASK		0x00008000
 #define TCLK_SHIFT		15
@@ -452,15 +412,9 @@
 #define MV_DRBL_PCIE_TO_CPU	0
 #define MV_DRBL_CPU_TO_PCIE	1
 
-#if defined(SOC_MV_FREY)
-#define MV_DRBL_CAUSE(d,u)	(0x60 + 0x20 * (d) + 0x8 * (u))
-#define MV_DRBL_MASK(d,u)	(0x60 + 0x20 * (d) + 0x8 * (u) + 0x4)
-#define MV_DRBL_MSG(m,d,u)	(0x8 * (u) + 0x20 * (d) + 0x4 * (m))
-#else
 #define MV_DRBL_CAUSE(d,u)	(0x10 * (u) + 0x8 * (d))
 #define MV_DRBL_MASK(d,u)	(0x10 * (u) + 0x8 * (d) + 0x4)
 #define MV_DRBL_MSG(m,d,u)	(0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30)
-#endif
 
 /*
  * SCU

Modified: head/sys/arm/mv/mvwin.h
==============================================================================
--- head/sys/arm/mv/mvwin.h	Fri Mar 17 12:45:53 2017	(r315450)
+++ head/sys/arm/mv/mvwin.h	Fri Mar 17 12:59:16 2017	(r315451)
@@ -52,25 +52,16 @@
 /* SRAM */
 #define MV_CESA_SRAM_BASE	0xF1100000
 
-/* AXI Regs */
-#ifdef SOC_MV_DOVE
-#define MV_AXI_PHYS_BASE	0xF1800000
-#define MV_AXI_BASE		MV_AXI_PHYS_BASE
-#define MV_AXI_SIZE		(16 * 1024 * 1024)	/* 16 MB */
-#endif
-
 /*
  * External devices: 0x80000000, 1 GB (VA == PA)
  * Includes Device Bus, PCI and PCIE.
  */
 #if defined(SOC_MV_ORION)
 #define MV_PCI_PORTS	2	/* 1x PCI + 1x PCIE */
-#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_FREY)
+#elif defined(SOC_MV_KIRKWOOD)
 #define MV_PCI_PORTS	1	/* 1x PCIE */
 #elif defined(SOC_MV_DISCOVERY)
 #define MV_PCI_PORTS	8	/* 8x PCIE */
-#elif defined(SOC_MV_DOVE) || defined(SOC_MV_LOKIPLUS)
-#define MV_PCI_PORTS	2	/* 2x PCIE */
 #elif defined(SOC_MV_ARMADAXP)
 #define MV_PCI_PORTS	3	/* 3x PCIE */
 #elif defined(SOC_MV_ARMADA38X)
@@ -93,11 +84,7 @@
 #define MV_PCI_IO_SLICE_SIZE	(MV_PCI_IO_SIZE / MV_PCI_PORTS)
 #define MV_PCI_IO_SLICE(n)	(MV_PCI_IO_BASE + ((n) * MV_PCI_IO_SLICE_SIZE))
 
-#if defined(SOC_MV_FREY)
-#define MV_PCI_VA_MEM_BASE	MV_PCI_MEM_BASE
-#else
 #define MV_PCI_VA_MEM_BASE	0
-#endif
 #define MV_PCI_VA_IO_BASE	0
 
 /*
@@ -120,11 +107,7 @@
  * Integrated SoC peripherals addresses
  */
 #define MV_BASE			MV_PHYS_BASE	/* VA == PA mapping */
-#if defined(SOC_MV_DOVE)
-#define MV_DDR_CADR_BASE	(MV_AXI_BASE + 0x100)
-#elif defined(SOC_MV_LOKIPLUS)
-#define MV_DDR_CADR_BASE	(MV_BASE + 0xF1500)
-#elif defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
+#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
 #define MV_DDR_CADR_BASE	(MV_BASE + 0x20180)
 #else
 #define MV_DDR_CADR_BASE	(MV_BASE + 0x1500)
@@ -137,20 +120,16 @@
 #define MV_INTREGS_BASE		(MV_MBUS_BRIDGE_BASE + 0x80)
 #define MV_MP_CLOCKS_BASE	(MV_MBUS_BRIDGE_BASE + 0x700)
 #define MV_CPU_CONTROL_BASE	(MV_MBUS_BRIDGE_BASE + 0x1800)
-#elif !defined(SOC_MV_FREY)
+#else
 #define MV_MBUS_BRIDGE_BASE	(MV_BASE + 0x20000)
 #define MV_INTREGS_BASE		(MV_MBUS_BRIDGE_BASE + 0x80)
 #define MV_CPU_CONTROL_BASE	(MV_MBUS_BRIDGE_BASE + 0x100)
-#else
-#define MV_CPU_CONTROL_BASE	(MV_BASE + 0x10000)
 #endif
 
 #define MV_PCI_BASE		(MV_BASE + 0x30000)
 #define MV_PCI_SIZE		0x2000
 
-#if defined(SOC_MV_FREY)
-#define MV_PCIE_BASE		(MV_BASE + 0x8000)
-#elif defined(SOC_MV_ARMADA38X)
+#if defined(SOC_MV_ARMADA38X)
 #define	MV_PCIE_BASE		(MV_BASE + 0x80000)
 #else
 #define MV_PCIE_BASE		(MV_BASE + 0x40000)
@@ -193,26 +172,12 @@
 #endif
 
 #define MV_WIN_CPU_ATTR_SHIFT		8
-#if defined(SOC_MV_LOKIPLUS)
-#define MV_WIN_CPU_TARGET_SHIFT		0
-#define MV_WIN_CPU_ENABLE_BIT		(1 << 5)
-#else
 #define MV_WIN_CPU_TARGET_SHIFT		4
 #define MV_WIN_CPU_ENABLE_BIT		1
-#endif
 
-#if defined(SOC_MV_DOVE)
-#define MV_WIN_DDR_MAX			2
-#else /* SOC_MV_DOVE */
-#if defined(SOC_MV_LOKIPLUS)
-#define MV_WIN_DDR_BASE(n)		(0xc * (n) + 0x4)
-#define MV_WIN_DDR_SIZE(n)		(0xc * (n) + 0x0)
-#else /* SOC_MV_LOKIPLUS */
 #define MV_WIN_DDR_BASE(n)		(0x8 * (n) + 0x0)
 #define MV_WIN_DDR_SIZE(n)		(0x8 * (n) + 0x4)
-#endif /* SOC_MV_LOKIPLUS */
 #define MV_WIN_DDR_MAX			4
-#endif /* SOC_MV_DOVE */
 
 /*
  * These values are valid only for peripherals decoding windows
@@ -280,7 +245,7 @@
 #define MV_XOR_CHAN_MAX			2
 #define MV_XOR_NON_REMAP		4
 
-#if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DOVE)
+#if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_KIRKWOOD)
 #define MV_WIN_PCIE_TARGET(n)		4
 #define MV_WIN_PCIE_MEM_ATTR(n)		0xE8
 #define MV_WIN_PCIE_IO_ATTR(n)		0xE0
@@ -296,10 +261,6 @@
 #define MV_WIN_PCIE_TARGET(n)		4
 #define MV_WIN_PCIE_MEM_ATTR(n)		0x59
 #define MV_WIN_PCIE_IO_ATTR(n)		0x51
-#elif defined(SOC_MV_LOKIPLUS)
-#define MV_WIN_PCIE_TARGET(n)		(3 + (n))
-#define MV_WIN_PCIE_MEM_ATTR(n)		0x59
-#define MV_WIN_PCIE_IO_ATTR(n)		0x51
 #endif
 
 #define MV_WIN_PCI_TARGET		3

Modified: head/sys/conf/options.arm
==============================================================================
--- head/sys/conf/options.arm	Fri Mar 17 12:45:53 2017	(r315450)
+++ head/sys/conf/options.arm	Fri Mar 17 12:59:16 2017	(r315451)
@@ -60,10 +60,7 @@ SOC_IMX6		opt_global.h
 SOC_MV_ARMADAXP		opt_global.h
 SOC_MV_ARMADA38X	opt_global.h
 SOC_MV_DISCOVERY	opt_global.h
-SOC_MV_DOVE		opt_global.h
-SOC_MV_FREY		opt_global.h
 SOC_MV_KIRKWOOD		opt_global.h
-SOC_MV_LOKIPLUS		opt_global.h
 SOC_MV_ORION		opt_global.h
 SOC_OMAP3		opt_global.h
 SOC_OMAP4		opt_global.h

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