svn commit: r314599 - head/sys/gnu/dts/arm
Emmanuel Vadot
manu at bidouilliste.com
Sat Mar 4 00:31:45 UTC 2017
Hi Ruslan,
Could you revert please ?
GNU DTS are from vendor import and I plan to update to linux 4.10 soon
(like this week), and this will complicate merge.
Thanks,
On Fri, 3 Mar 2017 14:17:07 +0000 (UTC)
Ruslan Bukin <br at FreeBSD.org> wrote:
> Author: br
> Date: Fri Mar 3 14:17:07 2017
> New Revision: 314599
> URL: https://svnweb.freebsd.org/changeset/base/314599
>
> Log:
> Import latest vendor DTS files for Intel Arria 10.
>
> Modified:
> head/sys/gnu/dts/arm/socfpga_arria10.dtsi
> head/sys/gnu/dts/arm/socfpga_arria10_socdk.dtsi
> head/sys/gnu/dts/arm/socfpga_arria10_socdk_sdmmc.dts
>
> Modified: head/sys/gnu/dts/arm/socfpga_arria10.dtsi
> ==============================================================================
> --- head/sys/gnu/dts/arm/socfpga_arria10.dtsi Fri Mar 3 14:06:22 2017 (r314598)
> +++ head/sys/gnu/dts/arm/socfpga_arria10.dtsi Fri Mar 3 14:17:07 2017 (r314599)
> @@ -22,11 +22,6 @@
> #address-cells = <1>;
> #size-cells = <1>;
>
> - aliases {
> - serial0 = &uart0;
> - serial1 = &uart1;
> - };
> -
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -88,6 +83,14 @@
> };
> };
>
> + base_fpga_region {
> + #address-cells = <0x1>;
> + #size-cells = <0x1>;
> +
> + compatible = "fpga-region";
> + fpga-mgr = <&fpga_mgr>;
> + };
> +
> clkmgr at ffd04000 {
> compatible = "altr,clk-mgr";
> reg = <0xffd04000 0x1000>;
> @@ -405,6 +408,12 @@
> };
> };
>
> + socfpga_axi_setup: stmmac-axi-config {
> + snps,wr_osr_lmt = <0xf>;
> + snps,rd_osr_lmt = <0xf>;
> + snps,blen = <0 0 0 0 16 0 0>;
> + };
> +
> gmac0: ethernet at ff800000 {
> compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
> altr,sysmgr-syscon = <&sysmgr 0x44 0>;
> @@ -421,6 +430,7 @@
> clock-names = "stmmaceth";
> resets = <&rst EMAC0_RESET>;
> reset-names = "stmmaceth";
> + snps,axi-config = <&socfpga_axi_setup>;
> status = "disabled";
> };
>
> @@ -440,6 +450,7 @@
> clock-names = "stmmaceth";
> resets = <&rst EMAC1_RESET>;
> reset-names = "stmmaceth";
> + snps,axi-config = <&socfpga_axi_setup>;
> status = "disabled";
> };
>
> @@ -457,6 +468,7 @@
> rx-fifo-depth = <16384>;
> clocks = <&l4_mp_clk>;
> clock-names = "stmmaceth";
> + snps,axi-config = <&socfpga_axi_setup>;
> status = "disabled";
> };
>
> @@ -517,6 +529,15 @@
> };
> };
>
> + fpga_mgr: fpga-mgr at ffd03000 {
> + compatible = "altr,socfpga-a10-fpga-mgr";
> + reg = <0xffd03000 0x100
> + 0xffcfe400 0x20>;
> + clocks = <&l4_mp_clk>;
> + resets = <&rst FPGAMGR_RESET>;
> + reset-names = "fpgamgr";
> + };
> +
> i2c0: i2c at ffc02200 {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -567,15 +588,24 @@
> status = "disabled";
> };
>
> - sdr: sdr at ffc25000 {
> - compatible = "syscon";
> - reg = <0xffcfb100 0x80>;
> + spi1: spi at ffda5000 {
> + compatible = "snps,dw-apb-ssi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0xffda5000 0x100>;
> + interrupts = <0 102 4>;
> + num-chipselect = <4>;
> + bus-num = <0>;
> + /*32bit_access;*/
> + tx-dma-channel = <&pdma 16>;
> + rx-dma-channel = <&pdma 17>;
> + clocks = <&spi_m_clk>;
> + status = "disabled";
> };
>
> - sdramedac {
> - compatible = "altr,sdram-edac-a10";
> - altr,sdr-syscon = <&sdr>;
> - interrupts = <0 2 4>, <0 0 4>;
> + sdr: sdr at ffc25000 {
> + compatible = "altr,sdr-ctl", "syscon";
> + reg = <0xffcfb100 0x80>;
> };
>
> L2: l2-cache at fffff000 {
> @@ -584,6 +614,9 @@
> interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
> cache-unified;
> cache-level = <2>;
> + prefetch-data = <1>;
> + prefetch-instr = <1>;
> + arm,shared-override;
> };
>
> mmc: dwmmc0 at ff808000 {
> @@ -598,6 +631,19 @@
> status = "disabled";
> };
>
> + nand: nand at ffb90000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
> + reg = <0xffb90000 0x72000>,
> + <0xffb80000 0x10000>;
> + reg-names = "nand_data", "denali_reg";
> + interrupts = <0 99 4>;
> + dma-mask = <0xffffffff>;
> + clocks = <&nand_clk>;
> + status = "disabled";
> + };
> +
> ocram: sram at ffe00000 {
> compatible = "mmio-sram";
> reg = <0xffe00000 0x40000>;
> @@ -610,17 +656,76 @@
> #size-cells = <1>;
> interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
> <0 0 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> ranges;
>
> + sdramedac {
> + compatible = "altr,sdram-edac-a10";
> + altr,sdr-syscon = <&sdr>;
> + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
> + <49 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> l2-ecc at ffd06010 {
> compatible = "altr,socfpga-a10-l2-ecc";
> reg = <0xffd06010 0x4>;
> + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
> + <32 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> ocram-ecc at ff8c3000 {
> compatible = "altr,socfpga-a10-ocram-ecc";
> reg = <0xff8c3000 0x400>;
> + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
> + <33 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + emac0-rx-ecc at ff8c0800 {
> + compatible = "altr,socfpga-eth-mac-ecc";
> + reg = <0xff8c0800 0x400>;
> + altr,ecc-parent = <&gmac0>;
> + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
> + <36 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + emac0-tx-ecc at ff8c0c00 {
> + compatible = "altr,socfpga-eth-mac-ecc";
> + reg = <0xff8c0c00 0x400>;
> + altr,ecc-parent = <&gmac0>;
> + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
> + <37 IRQ_TYPE_LEVEL_HIGH>;
> };
> +
> + dma-ecc at ff8c8000 {
> + compatible = "altr,socfpga-dma-ecc";
> + reg = <0xff8c8000 0x400>;
> + altr,ecc-parent = <&pdma>;
> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
> + <42 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + usb0-ecc at ff8c8800 {
> + compatible = "altr,socfpga-usb-ecc";
> + reg = <0xff8c8800 0x400>;
> + altr,ecc-parent = <&usb0>;
> + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
> + <34 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + qspi: spi at ff809000 {
> + compatible = "cdns,qspi-nor";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0xff809000 0x100>,
> + <0xffa00000 0x100000>;
> + interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
> + cdns,fifo-depth = <128>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x00000000>;
> + clocks = <&qspi_clk>;
> + status = "disabled";
> };
>
> rst: rstmgr at ffd05000 {
>
> Modified: head/sys/gnu/dts/arm/socfpga_arria10_socdk.dtsi
> ==============================================================================
> --- head/sys/gnu/dts/arm/socfpga_arria10_socdk.dtsi Fri Mar 3 14:06:22 2017 (r314598)
> +++ head/sys/gnu/dts/arm/socfpga_arria10_socdk.dtsi Fri Mar 3 14:17:07 2017 (r314599)
> @@ -20,9 +20,14 @@
> model = "Altera SOCFPGA Arria 10";
> compatible = "altr,socfpga-arria10", "altr,socfpga";
>
> + aliases {
> + ethernet0 = &gmac0;
> + serial0 = &uart1;
> + };
> +
> chosen {
> bootargs = "earlyprintk";
> - stdout-path = "serial1:115200n8";
> + stdout-path = "serial0:115200n8";
> };
>
> memory {
> @@ -31,6 +36,30 @@
> reg = <0x0 0x40000000>; /* 1GB */
> };
>
> + a10leds {
> + compatible = "gpio-leds";
> +
> + a10sr_led0 {
> + label = "a10sr-led0";
> + gpios = <&a10sr_gpio 0 1>;
> + };
> +
> + a10sr_led1 {
> + label = "a10sr-led1";
> + gpios = <&a10sr_gpio 1 1>;
> + };
> +
> + a10sr_led2 {
> + label = "a10sr-led2";
> + gpios = <&a10sr_gpio 2 1>;
> + };
> +
> + a10sr_led3 {
> + label = "a10sr-led3";
> + gpios = <&a10sr_gpio 3 1>;
> + };
> + };
> +
> soc {
> clkmgr at ffd04000 {
> clocks {
> @@ -70,6 +99,31 @@
> status = "okay";
> };
>
> +&gpio1 {
> + status = "okay";
> +};
> +
> +&spi1 {
> + status = "okay";
> +
> + resource-manager at 0 {
> + compatible = "altr,a10sr";
> + reg = <0>;
> + spi-max-frequency = <100000>;
> + /* low-level active IRQ at GPIO1_5 */
> + interrupt-parent = <&portb>;
> + interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + a10sr_gpio: gpio-controller {
> + compatible = "altr,a10sr-gpio";
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> + };
> +};
> +
> &i2c1 {
> speed-mode = <0>;
> status = "okay";
> @@ -91,6 +145,11 @@
> compatible = "dallas,ds1339";
> reg = <0x68>;
> };
> +
> + ltc at 5c {
> + compatible = "ltc2977";
> + reg = <0x5c>;
> + };
> };
>
> &uart1 {
> @@ -100,3 +159,7 @@
> &usb0 {
> status = "okay";
> };
> +
> +&watchdog1 {
> + status = "okay";
> +};
>
> Modified: head/sys/gnu/dts/arm/socfpga_arria10_socdk_sdmmc.dts
> ==============================================================================
> --- head/sys/gnu/dts/arm/socfpga_arria10_socdk_sdmmc.dts Fri Mar 3 14:06:22 2017 (r314598)
> +++ head/sys/gnu/dts/arm/socfpga_arria10_socdk_sdmmc.dts Fri Mar 3 14:17:07 2017 (r314599)
> @@ -25,3 +25,15 @@
> broken-cd;
> bus-width = <4>;
> };
> +
> +&eccmgr {
> + sdmmca-ecc at ff8c2c00 {
> + compatible = "altr,socfpga-sdmmc-ecc";
> + reg = <0xff8c2c00 0x400>;
> + altr,ecc-parent = <&mmc>;
> + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
> + <47 IRQ_TYPE_LEVEL_HIGH>,
> + <16 IRQ_TYPE_LEVEL_HIGH>,
> + <48 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +};
--
Emmanuel Vadot <manu at bidouilliste.com> <manu at freebsd.org>
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