svn commit: r314389 - in head/sys: arm/altera/socfpga arm/conf boot/fdt/dts/arm
Andrew Turner
andrew at fubar.geek.nz
Tue Feb 28 14:20:35 UTC 2017
On Tue, 28 Feb 2017 14:02:16 +0000 (UTC)
Ruslan Bukin <br at FreeBSD.org> wrote:
> Author: br
> Date: Tue Feb 28 14:02:16 2017
> New Revision: 314389
> URL: https://svnweb.freebsd.org/changeset/base/314389
>
> Log:
> Add support for Intel Arria 10 SoC Development Kit.
> Use standard DTS files for SOCKIT and SOCDK.
>
> Sponsored by: DARPA, AFRL
>
> Added:
> head/sys/arm/conf/SOCDK (contents, props changed)
> head/sys/arm/conf/SOCFPGA (contents, props changed)
> head/sys/boot/fdt/dts/arm/socfpga_arria10_socdk_sdmmc.dts
> (contents, props changed)
> head/sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_beri_sdmmc.dts
> (contents, props changed)
> head/sys/boot/fdt/dts/arm/socfpga_cyclone5_sockit_sdmmc.dts
> (contents, props changed) Deleted: head/sys/arm/conf/SOCKIT.common
> head/sys/boot/fdt/dts/arm/socfpga-sockit-beri.dts
> head/sys/boot/fdt/dts/arm/socfpga-sockit.dts
> head/sys/boot/fdt/dts/arm/socfpga.dtsi Modified:
> head/sys/arm/altera/socfpga/socfpga_machdep.c
> head/sys/arm/altera/socfpga/socfpga_manager.c
> head/sys/arm/altera/socfpga/socfpga_mp.c
> head/sys/arm/altera/socfpga/socfpga_mp.h
> head/sys/arm/altera/socfpga/socfpga_rstmgr.c
> head/sys/arm/altera/socfpga/socfpga_rstmgr.h
> head/sys/arm/conf/SOCKIT
> head/sys/arm/conf/SOCKIT-BERI
>
> Modified: head/sys/arm/altera/socfpga/socfpga_machdep.c
> ==============================================================================
> --- head/sys/arm/altera/socfpga/socfpga_machdep.c Tue Feb 28
> 12:05:58 2017 (r314388) +++
> head/sys/arm/altera/socfpga/socfpga_machdep.c Tue Feb 28
> 14:02:16 2017 (r314389) @@ -1,5 +1,5 @@ /*-
> - * Copyright (c) 2014 Ruslan Bukin <br at bsdpad.com>
> + * Copyright (c) 2014-2017 Ruslan Bukin <br at bsdpad.com>
> * All rights reserved.
> *
> * This software was developed by SRI International and the
> University of @@ -83,24 +83,43 @@ socfpga_devmap_init(platform_t plat)
> return (0);
> }
>
> +static int
> +socfpga_a10_devmap_init(platform_t plat)
You should create a SOC_ALTERA_ARRIA10 (or similar) option and use it
to conditionally compile this code.
> +{
> +
> + /* UART */
> + devmap_add_entry(0xffc00000, 0x100000);
> +
> + /* USB OTG */
> + devmap_add_entry(0xffb00000, 0x100000);
> +
> + /* dwmmc */
> + devmap_add_entry(0xff800000, 0x100000);
> +
> + /* scu */
> + devmap_add_entry(0xfff00000, 0x100000);
> +
> + return (0);
> +}
> +
> static void
> -socfpga_cpu_reset(platform_t plat)
> +_socfpga_cpu_reset(platform_t plat, uint32_t reg)
Why are you passing the platform_t into this? And reg should be a
bus_size_t.
> {
> uint32_t paddr;
> bus_addr_t vaddr;
> phandle_t node;
>
> - if (rstmgr_warmreset() == 0)
> + if (rstmgr_warmreset(reg) == 0)
> goto end;
>
> - node = OF_finddevice("rstmgr");
> + node = OF_finddevice("/soc/rstmgr");
> if (node == -1)
> goto end;
>
> if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0)
> { if (bus_space_map(fdtbus_bs_tag, paddr, 0x8, 0, &vaddr) == 0) {
> bus_space_write_4(fdtbus_bs_tag, vaddr,
> - RSTMGR_CTRL, CTRL_SWWARMRSTREQ);
> + reg, CTRL_SWWARMRSTREQ);
> }
> }
>
> @@ -108,16 +127,38 @@ end:
> while (1);
> }
>
> +static void
> +socfpga_cpu_reset(platform_t plat)
> +{
> +
> + _socfpga_cpu_reset(plat, RSTMGR_CTRL);
> +}
> +
> +static void
> +socfpga_a10_cpu_reset(platform_t plat)
> +{
> +
> + _socfpga_cpu_reset(plat, RSTMGR_A10_CTRL);
> +}
these two and the methods below should be under SOC_ checks.
> +
> static platform_method_t socfpga_methods[] = {
> PLATFORMMETHOD(platform_devmap_init,
> socfpga_devmap_init), PLATFORMMETHOD(platform_cpu_reset,
> socfpga_cpu_reset), -
> #ifdef SMP
> PLATFORMMETHOD(platform_mp_setmaxid,
> socfpga_mp_setmaxid), PLATFORMMETHOD(platform_mp_start_ap,
> socfpga_mp_start_ap), #endif
> -
> PLATFORMMETHOD_END,
> };
> +FDT_PLATFORM_DEF(socfpga, "socfpga", 0, "altr,socfpga-cyclone5",
> 200);
> -FDT_PLATFORM_DEF(socfpga, "socfpga", 0, "altr,socfpga", 0);
> +static platform_method_t socfpga_a10_methods[] = {
> + PLATFORMMETHOD(platform_devmap_init,
> socfpga_a10_devmap_init),
> + PLATFORMMETHOD(platform_cpu_reset,
> socfpga_a10_cpu_reset), +#ifdef SMP
> + PLATFORMMETHOD(platform_mp_setmaxid,
> socfpga_mp_setmaxid),
> + PLATFORMMETHOD(platform_mp_start_ap,
> socfpga_a10_mp_start_ap), +#endif
> + PLATFORMMETHOD_END,
> +};
> +FDT_PLATFORM_DEF(socfpga_a10, "socfpga", 0, "altr,socfpga-arria10",
> 200);
>
> Modified: head/sys/arm/altera/socfpga/socfpga_manager.c
> ==============================================================================
> --- head/sys/arm/altera/socfpga/socfpga_manager.c Tue Feb 28
> 12:05:58 2017 (r314388) +++
> head/sys/arm/altera/socfpga/socfpga_manager.c Tue Feb 28
> 14:02:16 2017 (r314389) @@ -377,7 +377,7 @@
> fpgamgr_probe(device_t dev) if (!ofw_bus_status_okay(dev)) return
> (ENXIO);
> - if (!ofw_bus_is_compatible(dev, "altr,fpga-mgr"))
> + if (!ofw_bus_is_compatible(dev, "altr,socfpga-fpga-mgr"))
> return (ENXIO);
>
> device_set_desc(dev, "FPGA Manager");
>
> Modified: head/sys/arm/altera/socfpga/socfpga_mp.c
> ==============================================================================
> --- head/sys/arm/altera/socfpga/socfpga_mp.c Tue Feb 28
> 12:05:58 2017 (r314388) +++
> head/sys/arm/altera/socfpga/socfpga_mp.c Tue Feb 28 14:02:16
> 2017 (r314389) @@ -1,5 +1,5 @@ /*-
> - * Copyright (c) 2014 Ruslan Bukin <br at bsdpad.com>
> + * Copyright (c) 2014-2017 Ruslan Bukin <br at bsdpad.com>
> * All rights reserved.
> *
> * This software was developed by SRI International and the
> University of @@ -50,8 +50,10 @@ __FBSDID("$FreeBSD$");
> #include <machine/platformvar.h>
>
> #include <arm/altera/socfpga/socfpga_mp.h>
> +#include <arm/altera/socfpga/socfpga_rstmgr.h>
>
> #define SCU_PHYSBASE 0xFFFEC000
> +#define SCU_PHYSBASE_A10 0xFFFFC000
> #define SCU_SIZE 0x100
>
> #define SCU_CONTROL_REG 0x00
> @@ -69,11 +71,12 @@ __FBSDID("$FreeBSD$");
>
> #define RSTMGR_PHYSBASE 0xFFD05000
> #define RSTMGR_SIZE 0x100
> -#define MPUMODRST 0x10
> -#define MPUMODRST_CPU1 (1 << 1)
>
> #define RAM_PHYSBASE 0x0
> -#define RAM_SIZE 0x1000
> +#define RAM_SIZE 0x1000
> +
> +#define SOCFPGA_SOCKIT 1
> +#define SOCFPGA_SOCDK 2
>
> extern char *mpentry_addr;
> static void socfpga_trampoline(void);
> @@ -109,15 +112,22 @@ socfpga_mp_setmaxid(platform_t plat)
> mp_maxid = ncpu - 1;
> }
>
> -void
> -socfpga_mp_start_ap(platform_t plat)
> +
> +static void
> +_socfpga_mp_start_ap(platform_t plat, uint32_t platid)
> {
> bus_space_handle_t scu, rst, ram;
> int reg;
>
> - if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE,
> - SCU_SIZE, 0, &scu) != 0)
> + if (platid == SOCFPGA_SOCDK) {
This should become a switch, with options protected by the SOC_
options, and a panic in the default case.
> + if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE_A10,
> + SCU_SIZE, 0, &scu) != 0)
> panic("Couldn't map the SCU\n");
The indentation here is odd.
> + } else {
> + if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE,
> + SCU_SIZE, 0, &scu) != 0)
> + panic("Couldn't map the SCU\n");
> + }
> if (bus_space_map(fdtbus_bs_tag, RSTMGR_PHYSBASE,
> RSTMGR_SIZE, 0, &rst) != 0)
> panic("Couldn't map the reset manager (RSTMGR)\n");
> @@ -139,7 +149,13 @@ socfpga_mp_start_ap(platform_t plat)
> bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, reg);
>
> /* Put CPU1 to reset state */
> - bus_space_write_4(fdtbus_bs_tag, rst, MPUMODRST,
> MPUMODRST_CPU1);
> + if (platid == SOCFPGA_SOCDK) {
> + bus_space_write_4(fdtbus_bs_tag, rst,
> + RSTMGR_A10_MPUMODRST, MPUMODRST_CPU1);
> + } else {
> + bus_space_write_4(fdtbus_bs_tag, rst,
> + RSTMGR_MPUMODRST, MPUMODRST_CPU1);
> + }
>
> /* Enable the SCU, then clean the cache on this core */
> reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
> @@ -154,7 +170,13 @@ socfpga_mp_start_ap(platform_t plat)
> dcache_wbinv_poc_all();
>
> /* Put CPU1 out from reset */
> - bus_space_write_4(fdtbus_bs_tag, rst, MPUMODRST, 0);
> + if (platid == SOCFPGA_SOCDK) {
> + bus_space_write_4(fdtbus_bs_tag, rst,
> + RSTMGR_A10_MPUMODRST, 0);
> + } else {
> + bus_space_write_4(fdtbus_bs_tag, rst,
> + RSTMGR_MPUMODRST, 0);
> + }
>
> dsb();
> sev();
> @@ -163,3 +185,18 @@ socfpga_mp_start_ap(platform_t plat)
> bus_space_unmap(fdtbus_bs_tag, rst, RSTMGR_SIZE);
> bus_space_unmap(fdtbus_bs_tag, ram, RAM_SIZE);
> }
> +
> +void
> +socfpga_a10_mp_start_ap(platform_t plat)
> +{
> +
> + _socfpga_mp_start_ap(plat, SOCFPGA_SOCDK);
> +}
> +
> +void
> +socfpga_mp_start_ap(platform_t plat)
> +{
> +
> + _socfpga_mp_start_ap(plat, SOCFPGA_SOCKIT);
> +}
> +
>
> Modified: head/sys/arm/altera/socfpga/socfpga_mp.h
> ==============================================================================
> --- head/sys/arm/altera/socfpga/socfpga_mp.h Tue Feb 28
> 12:05:58 2017 (r314388) +++
> head/sys/arm/altera/socfpga/socfpga_mp.h Tue Feb 28 14:02:16
> 2017 (r314389) @@ -30,5 +30,6 @@
> void socfpga_mp_setmaxid(platform_t);
> void socfpga_mp_start_ap(platform_t);
> +void socfpga_a10_mp_start_ap(platform_t);
>
> #endif /* _SOCFPGA_MP_H_ */
>
> Modified: head/sys/arm/altera/socfpga/socfpga_rstmgr.c
> ==============================================================================
> --- head/sys/arm/altera/socfpga/socfpga_rstmgr.c Tue Feb 28
> 12:05:58 2017 (r314388) +++
> head/sys/arm/altera/socfpga/socfpga_rstmgr.c Tue Feb 28
> 14:02:16 2017 (r314389) @@ -1,5 +1,5 @@ /*-
> - * Copyright (c) 2014 Ruslan Bukin <br at bsdpad.com>
> + * Copyright (c) 2014-2017 Ruslan Bukin <br at bsdpad.com>
> * All rights reserved.
> *
> * This software was developed by SRI International and the
> University of @@ -166,7 +166,7 @@ rstmgr_sysctl(SYSCTL_HANDLER_ARGS)
> }
>
> int
> -rstmgr_warmreset(void)
> +rstmgr_warmreset(uint32_t reg)
> {
> struct rstmgr_softc *sc;
>
> @@ -175,8 +175,7 @@ rstmgr_warmreset(void)
> return (1);
>
> /* Request warm reset */
> - WRITE4(sc, RSTMGR_CTRL,
> - CTRL_SWWARMRSTREQ);
> + WRITE4(sc, reg, CTRL_SWWARMRSTREQ);
>
> return (0);
> }
> @@ -214,6 +213,7 @@ rstmgr_probe(device_t dev)
> return (ENXIO);
>
> device_set_desc(dev, "Reset Manager");
> +
> return (BUS_PROBE_DEFAULT);
> }
>
>
> Modified: head/sys/arm/altera/socfpga/socfpga_rstmgr.h
> ==============================================================================
> --- head/sys/arm/altera/socfpga/socfpga_rstmgr.h Tue Feb 28
> 12:05:58 2017 (r314388) +++
> head/sys/arm/altera/socfpga/socfpga_rstmgr.h Tue Feb 28
> 14:02:16 2017 (r314389) @@ -35,6 +35,7 @@ #define
> CTRL_SWWARMRSTREQ (1 << 1) /* Trigger warm reset */
> #define RSTMGR_COUNTS 0x8 /* Reset
> Cycles Count */ #define RSTMGR_MPUMODRST 0x10 /*
> MPU Module Reset */ +#define
> MPUMODRST_CPU1 (1 << 1) #define
> RSTMGR_PERMODRST 0x14 /* Peripheral Module Reset */
> #define RSTMGR_PER2MODRST 0x18 /* Peripheral 2
> Module Reset */ #define RSTMGR_BRGMODRST 0x1C /*
> Bridge Module Reset */ @@ -43,4 +44,7 @@ #define
> BRGMODRST_HPS2FPGA (1 << 0) #define
> RSTMGR_MISCMODRST 0x20 /* Miscellaneous Module Reset */
> -int rstmgr_warmreset(void); +#define
> RSTMGR_A10_CTRL 0xC /* Control */
> +#define RSTMGR_A10_MPUMODRST 0x20 /* MPU Module
> Reset */ + +int rstmgr_warmreset(uint32_t reg);
>
> Added: head/sys/arm/conf/SOCDK
> ==============================================================================
> --- /dev/null 00:00:00 1970 (empty, because file is
> newly added) +++ head/sys/arm/conf/SOCDK Tue Feb 28 14:02:16
> 2017 (r314389) @@ -0,0 +1,30 @@
> +#
> +# Kernel configuration for Altera Arria10 SOC Development Kit.
> +#
> +# For more information on this file, please read the config(5)
> manual page, +# and/or the handbook section on Kernel Configuration
> Files: +#
> +#
> http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
> +# +# The handbook is also available locally
> in /usr/share/doc/handbook +# if you've installed the doc
> distribution, otherwise always see the +# FreeBSD World Wide Web
> server (http://www.FreeBSD.org/) for the +# latest information.
> +#
> +# An exhaustive list of options and more detailed explanations of the
> +# device lines is also present in the ../../conf/NOTES and NOTES
> files. +# If you are in doubt as to the purpose or necessity of a
> line, check first +# in NOTES.
> +#
> +# $FreeBSD$
> +
> +#NO_UNIVERSE
> +
> +include "SOCFPGA"
> +ident SOCDK
> +
> +options ROOTDEVNAME=\"ufs:/dev/mmcsd0s4\"
> +
> +# Flattened Device Tree
> +options FDT_DTB_STATIC
> +makeoptions FDT_DTS_FILE=socfpga_arria10_socdk_sdmmc.dts
Can we move away from ROOTDEVNAME and FDT_DTB_STATIC? It stops this from
being used in a GENERIC kernel.
Andrew
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